Behavioral Modeling and Circuit Design of High Precision Low Power Dynamic Zoom ADC

Abstract

In this paper, a high-precision, energy-saving dynamic zoom ADC consisting of a 6-bit SAR ADC and a second-level Σ − ∆ modulator (SDM) is proposed. Non-ideal factors, including slew rate (SR), limited bandwidth and DC gain of the op-amp, and kT/C noise, mismatch of DAC capacitors, are analyzed with a behavioral model in Simulink to guide actual circuit design more accurately. The ADC parameters are adjusted and optimized by model simulation. Because the DAC capacitors mismatch produces harmonic distortion, the DWA technique is used. A new digital combined circuit is proposed to minimize power consumption. To further improve its energy efficiency, a gain enhancement current mirror OTA is designed and the SAR ADC adopts upper plate sampling technique. The layout of zoom ADC occupies 0.856 mm2 in 65 nm techniques. It achieves 109.2 dB SNDR, 17.84 bits ENOB at 1 kHz signal bandwidth and consumes only 0.233 mW.