Buried Oxide Layer Research Articles

New Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET

We report a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations. The study shows the remarkable role of the SiO2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si1-xGex. We found very specific annealing conditions to relax SGOI while keeping a homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO2 at this temperature, which would allow layer-by-layer matter redistribution. Remarkably, the Si layer epitaxially grown on relaxed SGOI remains fully strained with -0.85% tensile strain. The absence of strain sharing (between Si1-xGex and Si) is explained by the rigidity of the Si1-xGex/BOX interface at low temperature. Elastic simulations of the real system show that, because of the very specific elastic characteristics of SiO2, there are unique experimental conditions that both relax Si1-xGex and keep Si strained. Various epitaxial processes could be revisited in light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switch applications and for many other applications.

Experimental investigation on total-ionizing-dose radiation effects on the electrical properties of SOI-LIGBT

In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative shift of the Vth. However, at the same overdrive voltage (Vov = Vg − Vth), the ICE at small VCE increases and the ICE at high VCE decreases after irradiation. The distinctive response of the out-put characteristics after irradiation is ascribed to the positive trapped charges in the field oxide (FOX) layer and the buried oxide (BOX) layer. The inimitable out-put behavior occurs at whatever the sign of the gate bias voltage during irradiation. The degradation mechanisms of the TID effects on the SOI-LIGBT are further analyzed and confirmed by simulation.

Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric

In this paper, for the first time we proposed a novel GaAs1-xSbx-on-Insulator (GASOI) FinFET on GaAS substrate using well calibrated simulation models. Impact of this novel channel material GaAs1-xSbx in FinFET performance is thoroughly investigated and optimized accordingly. The acquired results of the proposed device show a significant improvement in ON current with smaller OFF current, which in turn boosts ION/IOFF ratio as compared to the earlier reported InGa1-xAsx and InGa1-xSbx FinFET. A maximum transconductance (gm) of ∼1.3 mS/μm is achieved that signifies a higher intrinsic gain of the proposed device. The performance optimization can be done by varying various device dimensional parameters such as width and height of the Fin, channel length, along with the gate metal work-function. We have also investigated the impact of interface trap charges in the device performance and to mitigate the effect of random dopants, a novel idea to implement a Hetero Buried Oxide (BOX) layer over the GaAs1-xSbx SOI FinFET is discussed.

A lithography-free approach to create Si nanomembranes on flexible substrates

We demonstrate a lithography-free approach to create a crystalline Si nanomembrane (NM) on a flexible polydimethylsiloxane (PDMS) substrate, and to induce uniaxially tensile strain in the Si NM by mechanically stretching its host PDMS substrate. We start from a commercial silicon-on-insulator (SOI) wafer, remove the buried oxide (BOX) layer using hydrofluoric acid (HF), and transfer the weakly bonded Si NM onto a PDMS substrate by stamping. Flat and smooth Si NMs are created on PDMS substrates by this method, and the typical area of each crack-free region is larger than 100 μm × 100 μm. The root mean square (RMS) roughness of the crack-free regions of a transferred Si NM, as determined by atomic force microscopy (AFM), is typically 0.4–0.5 nm. Using x-ray diffraction (XRD) characterization, we confirm that the Si NM transferred on a PDMS substrate exhibits high crystalline quality that is compatible for device fabrication. We introduce tensile strain in the Si NM by stretching the PDMS substrate where the Si NM is hosted using a home-made mechanical tool. Raman spectroscopy analysis reveals that uniaxial tensile strain up to 1.0% is introduced along the <110> direction of the Si(001) NM. This work suggests that Si NMs created by this lithography-free approach are promising for applications in electronics and optoelectronics.

A Simple Proposal to Reduce Self-heating Effect in SOI MOSFETs

In this work, we aim to design a silicon on insulator MOSFET in which the self-heating effect is fully removed. Within the proposed scheme, a T-shaped 4H-SiC region is embedded in the buried oxide layer, extended from the silicon drift region towards the substrate providing a heating pathway to improve the low thermal conductivity of the oxide. This T-shaped 4H-SiC part can absorb heat from the active region and transfer it to the substrate area. Therefore, heat dissipation rising from the high gate and drain bias in MOSFETs are reduced. Simulations show that in addition to the maximum lattice temperature that is brought from ~ 694 K to ~ 366 K, DC and AC characteristics of the device have also improved drastically. The proposed transistor demonstrates lower negative differential resistance, more carrier mobility, higher saturation current, higher DC Transconductance, less delay time, and higher cut-off frequency compared to conventional silicon on insulator MOSFET. These promising properties and competitive advantages propose the designed device as a reliable alternative for conventional MOSFETs in high power and RF applications.

Metal based grating coupler on a thin-film lithium niobate waveguide.

Thin-film lithium niobate (LN) has been proved to be an excellent platform for building compact active and nonlinear photonic components on a chip. The coupling of a sub-micron sized LN waveguide and a single-mode fiber remains as one challenging issue. An efficient grating coupler made of Au stripes on an LN ridge waveguide is demonstrated here. The fabrication of the grating is convenient, using just a standard lift-off process of metal films. The peak coupling efficiency of an optimized structure reaches 50.4%, i.e., -3 dB coupling loss, at 1.55 µm wavelength for the fundamental transverse-electrical mode, where the 1-dB coupling bandwidth is 58 nm. Experimentally, fabricated devices, with buried oxide layer thicknesses slightly off the optimal values, exhibit coupling efficiencies of 43.8% and 33.7% for 400 nm and 600 nm thick LN layers.

Novel failure traces beyond the barrier on the floating device

Failure Analysis (FA) on Fully Depleted Silicon on Insulator (FDSOI) device is challenging due to its unique structure with buried oxide layer. Typical failure analyses for the bulk device are not viable to isolate the fault location as the first step for the defect finding any more in such a FDSOI environment. Based on the in-depth study on structural limitation of the FDSOI device, this paper firstly reports novel approaches for the physical and electrical FA methodologies with the success stories for yield learning. Furthermore, we demonstrate the improvements of FA methods compared to the conventional ones and how new ideas are applied to the analysis procedure including the minute soft defect FA.

Simulation based study on parameter variation of Si0.9Ge0.1 junction‐less SELBOX FinFET for high‐performance application

AbstractIn this article, we present a high‐performance SiGe junctionless FinFET (JLFinFET) on insulator by selective growth of buried oxide (SELBOX) layer device with better electrostatics. The mole fraction x = 0.1, 0.2, 0.3, 0.4, 0.5, and 0.7 with fin width 10 nm and gate length of 20 nm are considered for simulation using technology computer aided design (TCAD) Sentaurus device. With Si0.9Ge0.1 JLFinFET on insulator by SELBOX layer, nearly an ideal subthreshold swing of 61.51 mV/decade and enhanced on‐current, off‐current has been achieved. Evaluation of on‐off current ratio, DIBL, SS for different parameters, such as doping concentration (1015‐1019/cm3), channel length (10‐40 nm), temperature (200‐700°K) on JLJFinFET on insulator by SELBOX layer are presented. Three‐dimensional device simulation using the TCAD software tool Sentaurus Device is used to simulate and the results are compared with a SELBOX JLFinFET.

Backward-Emitting Silicon Nitride Optical Phased Array Enabling Efficient Wavelength-Tuned Beam Steering

Silicon nitride (SiN) optical phased arrays (OPAs) have emerged as a potential alternative to their silicon counterparts, due to their potential use in enhanced solid-state light detection and ranging. Grating antennas based on a SiN waveguide suffer from a limited beam steering efficiency, owing to the relatively lower effective refractive index of the waveguide. To mitigate this limitation, we propose and demonstrate a backward-emitting SiN OPA incorporating a reinforced grating vector, which provides efficient wavelength-tuned beam steering along the longitudinal direction. Two backward-emitting OPAs were primarily characterized by their steering efficiency and the spectral emission for the main lobe, and they were compared with a forward-emitting device using a weakened grating vector. The results indicated that strengthening the grating vector for the antenna improved the beam steering efficiency but adversely affected the dependence of its directionality on the wavelength. The directionality was particularly inspected, with respect to major design parameters for the grating antennas, including the pitch and etch depth of a SiN grating, as well as the thickness of a buried oxide and SiN core layer. The proposed backward-emitting OPA scheme is expected to significantly promote its feasibility as an advanced beam scanning device.

A Special Total-Ionizing-Dose-Induced Short Channel Effect in Thin-Film PDSOI Technology: Phenomena, Analyses, and Models

A special total-ionizing-dose-induced short channel effect in thin-film partially depleted silicon-on-insulator (PDSOI) technology is found. Short devices suffer more significant total-ionizing-dose-induced threshold voltage shift of the front-gate main transistor. The devices under pass-gate (PG) bias show worse threshold voltage shift of the front-gate main transistor than the devices under ON bias, which reveal that the trapped charges in the buried oxide layer are more responsible for these phenomena. Through the simulation of the electric field under PG bias by TCAD, we found that devices with different lengths can be uniformly divided into four regions. Then we combined the partially full depletion model with charge-sharing model and made a qualitative analysis of this effect. On this basis, we proposed a quantitative analysis model. Through this model, we can calculate the threshold voltage shift of the front-gate main transistor through the threshold voltage shift of back-gate main transistor.

Improvement of Electrical Characteristics of SiGe Source Based Tunnel FET Device

Tunnel Field Effect Transistor (TFET) is one of the most promising alternative device for semiconductor technology and shows better performance as compared to the conventional MOS device in terms of subthreshold swing, OFF current, etc. In this paper, SiGe source-based Heterojunction Tunnel FET has been investigated to enhance the performance of the device in terms of ON current and ION/IOFF ratio. The use of spacers has also been studied for enhancing the drain current. The combination of low-k (SiO2) and a high-k (HfO2) hetero dielectric material have been studied for the use of gate dielectric material as well as at the buried oxide layer. The proposed device offers an ON current of 0.537 mA/μm and an OFF current of 14.4 fA/μm, with an excellent ION/IOFF ratio of 3.72 × 1010. The average subthreshold swing of 28.57 mV/decade has also been achieved, which makes the device steeper. The ambipolar currents have been suppressed and hence the electrical characteristics of the proposed device are improved. The validity of the proposed device has been done by using TCAD simulation tool.

High resolution, high channel count mid-infrared arrayed waveguide gratings in silicon.

Arrayed waveguide gratings (AWGs) working in the 4.7 µm wavelength range are reported on silicon-on-insulator waveguides with 1500 nm thick silicon and 2 µm thick buried oxide layers. For eight channel devices, three different channel spacings (200 GHz, 100 GHz, and 50 GHz) with cross talk levels of -32.31dB, -31.87dB, and -27.28dB and insertion loss levels of -1.43dB, -4.2dB, and -2.3dB, respectively, are demonstrated. Fourteen channel AWGs with 170 GHz channel spacing and 16 channel AWGs with 87 GHz channel spacing are shown to have a cross talk value of -21.67dB and -24.30dB and insertion loss value of -4.2dB and -3.8dB, respectively. Two AWGs with 10 nm difference in channel peak are designed, and the measurements show a 9.3 nm difference. The transmission spectrum shift as a function of temperature is found to be 0.22 nm/°C.

Micrometer-scale InP selectively grown on SOI for fully integrated Si-photonics

Practical applications of low-defect III–V materials grown on Si require large areas for patterning metal contacts and enhancing design flexibility. Here, we report selective area growth of bufferless and micrometer-scale InP on commercial (001)-oriented silicon-on-insulators. We obtained in-plane, centimeter-long and micrometer-wide InP single crystal stripes right atop the buried oxide layer through leveraging the lateral aspect ratio trapping (lateral ART) growth method. Using the extended InP grown by “lateral ART,” we inserted InGaAs quantum wells emitting at the telecom bands. Numerical simulation suggests that the micrometer-scale InP can support the fundamental TE mode with an ultra-low metal-induced propagation loss of 3.2 dB/cm when patterned into ridge waveguides and introducing metal contacts at both ends. Our results here represent a leap toward electrically driven III–V lasers seamlessly interfaced with Si-photonics.

Fabrication of Germanium-on-insulator in a Ge wafer with a crystalline Ge top layer and buried GeO2 layer by oxygen ion implantation

The paper reports fabrication of Germanium-on-Insulator (GeOI) wafer by Oxygen ion implantation of an undoped Ge wafer of orientation (100). O+ ions (energy 200 keV) were implanted to a fluence of 1.9 × 1018 ions-cm−2 and the implanted wafer was subjected to Rapid Thermal Annealing. The resulting wafer has a top crystalline Ge layer of ~ 220 nm thickness and resistivity ≈32 Ohm-cm and a buried Oxide layer (BOX) of crystalline GeO2 (thickness ≈0.62 μm). The crystalline GeO2 layer has hexagonal crystal structure with lattice constants close to the standard values. Raman Spectroscopy and cross-sectional electron microscopy established that the top Ge layer was recrystallized during annealing with a residual tensile strain of around +0.4% and an estimated dislocation density of 2.7 × 107cm−2. The crystallinity and electrical characteristics of the top layer and the quality of the BOX layer are such that it can be utilized for device fabrication.

Total ionization dose effects and compensation in a counting type double SOI pixel sensor

We are developing the monolithic pixel sensors based on a 0.2 μm fully-depleted Silicon-on-Insulator (SOI) technology. One of the major issues in the SOI device is the total ionization dose (TID) effects in high-radiation environment. We studied the TID effects on a fully functional counting type pixel sensor based on Double SOI process. The device was irradiated to different dose at different region, by an X-ray tube operated at 30 kV with copper target. The degradation of the SOI MOSFET characteristics and the pixel response have been studied. The SPICE simulations using the transistor model with TID dose were performed on the pixel amplifier-shaper-discriminator (ASD) circuit to understand the malfunction in circuit level. In double SOI sensor, the SOI2 layer could compensate the positive charge induced by TID in buried oxide (BOX) layer when negatively biased. Such a compensation effectiveness has been observed in a counting type pixel sensor CPIXTEG3b.

Suspended-ultrathin Si membrane on SOI: a novel structure to reduce thermal stress of GaN epilayer

A 30nm-thick suspended-ultrathin silicon membrane based on SOI (silicon-on-insulator) substrate for GAN epitaxial growth is fabricated and analysed. We demonstrate that thermal stress of GaN in the effective area on this novel substrate can be reduced 44% more than that in normal SOI substrate, which can reduce the dislocation and crack density in GaN. The absence of BOX (buried oxide) layer are confirmed as main factors to result in reduction of thermal stress in GaN layer. This work provides a promising approach to obtain high-quality GaN by utilizing mechanical structure.

Investigation of Buried-Well Potential Perturbation Effects on SEU in SOI DICE-Based Flip-Flop Under Proton Irradiation

The effects of buried-well potential perturbation under the buried-oxide (BOX) layer are studied in both a heavy-ion single event upset (SEU) test and a high-energy proton-SEU test of a silicon-on-insulator (SOI) dual interlocked storage cell (DICE)-based flip-flop. Their dependence on incident angle and back bias is discussed. We fabricated both DICE-based flip-flop and conventional flip-flop, which are designed as 80 000-stage shift-register chains. In a heavy-ion test, a considerable number of SEUs were observed at back bias exceeding 2.4 V, and a ten-times larger SEU-cross section was finally recorded at back bias of 3.0 V compared with the total active area of a DICE-based flip-flop cell. This marks the first case where DICE topology was found to be broken by buried-well potential perturbation on an SOI DICE-based flip-flop. In a proton test, one error was observed at back bias of 2.0 V. The SEU rate in the Van Allen belt at an altitude of 2300 km and an inclination of 90° was estimated as being once every 5 years.

Silicon nitride optical phased array based on a grating antenna enabling wavelength-tuned beam steering.

An optical phased array (OPA) in silicon nitride (SiN) is conspicuously highlighted as a vital alternative to its counterpart in silicon. However, a limited number of studies have been conducted on this array in terms of wavelength-tuned beam steering. A SiN OPA has been proposed and implemented with a grating antenna that incorporated an array of shallow-etched waveguides, rendering wavelength-tuned beam steering along the longitudinal direction. To accomplish a superior directionality on a wavelength-tuned beam steering, the spectral beam emission characteristics of the antenna have been explored from the viewpoint of a planar structure that entails a buried oxide (BOX), a SiN waveguide core, and an upper cladding. Two OPA devices having substantially different thicknesses of the resonant cavities, established by combining the BOX and SiN core, were considered theoretically and experimentally to scrutinize the spectral emission characteristics of the antenna on beam steering. Both of the fabricated OPA devices steered light by an angle of 7.4° along the longitudinal direction for a wavelength ranging from 1530 to 1630 nm, while they maintained a divergence angle of 0.2°×0.6° in the longitudinal and lateral directions. Meanwhile, the OPA fabricated on a substantially thick BOX layer featured a limited steering performance to attain a stabilized response over a broad spectral region. We examined the influence of the cavity thickness on the spectral response of the antenna in terms of optical thickness. Based on the two antenna characteristics, it was confirmed that the grating antenna emitted the beam with a higher efficiency when the optical thickness of the cavity corresponded to odd integer multiples of the quarter wavelength. This work is a considerable strategy for designing a stabilized SiN OPA over a desired spectral region.

Induction of Buried Oxide Layer in Substrate FD-SOI MOSFET for Improving the Digital and Analog Performance

This paper is about to compare the electrical performance of conventional FD-SOI MOSFET with the BOX integrated substrate SOI MOSFET. The performance is compared and contrasted with the help of electric field, energy band diagram, surface potential, gate material (variation of workfunction) and parasitic capacitances. On comparison the proposed structure shows high Ion/Ioff ratio, high RSP, lower sub-threshold slope and lower threshold voltage then the conventional FD-SOI MOSFET. The performance of the proposed structure is also studied by the variation of buried oxide (BOX) thickness and the overlapped SOI (LSOI) region. Interestingly, by decreasing the thickness of BOX and LSOI region, the leakage current is decreasing without affecting the on-state current and the threshold voltage, thus increasing the Ion/Ioff ratio and decreasing the sub-threshold slope. In addition, this work also shows the improved analog performance in terms of transconductance (gm), gate to drain capacitance (Cgd), gate to source capacitances (Cgs), and cut-off frequency as compared to conventional FD-SOI MOSFET. The comparative study shows that the proposed structure is compatible for the digital as well as analog application without affecting the current fabrication process flow of the conventional FD-SOI MOSFET. Sentaurus two-dimensional simulations are used to analyze the performance of the proposed structure.

Simulating of charge build-up in irradiated MOS/SOI transistors

The charge build-up in the interface of silicon / buried oxide in n-channel MOS/SOI transistors depending on their geometric parameters and electrical modes during ionizing irradiation is calculated with the use of the software Silvaco. It is shown that the electrical mode is most “harsh”, when during irradiation the voltage of +5 V is applied to drain and source electrodes and 0 V is applied to substrate, gate and channel feeding. The amount of the built-up charge can be substantially reduced by applying a negative bias to the substrate and by decreasing the thickness of the buried oxide layer.