Abstract
Measurements of a new type of substrate for the integration of the trap-rich interface passivation solution with the below-buried oxide functionalities required in fully-depleted (FD) Silicon-on-Insulator (SOI) nodes is presented. This is achieved by adding a second thin buried oxide (BOX2) layer in between the substrate and the trap-rich/BOX1/SOI stack. It is shown that the trap-rich layer above BOX2 can effectively passivate the parasitic surface conduction that would be induced below BOX2 if BOX2 remains thinner than 20 nm. This is proven through measurements of substrate losses and non-linearity of coplanar waveguide transmission lines, comparing the fabricated double-BOX samples to reference trap-rich and unpassivated high-resistivity substrates.
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