Buried Channel CCD Research Articles

Charge-coupled devices with submicron gaps

The fabrication of two-phase buried channel charge-coupled devices with 100 transfer electrodes is described. The gate electrodes were constructed using only one level of polysilicon and with interelectrode gaps of approximately 0.5 µm. The edge etch technique was employed to provide 750 A wide windows to the polysilicon layer and then etching the polysilicon structure through these windows to produce submicron gaps. The use of the device as an analog delay line was demonstrated with a typical transfer efficiency of 0.99992 at 5 MHz.

A new method for the two-dimensional calculation of the potential distribution in a buried-channel charge-coupled device: Theory and experimental verification

This paper describes a new method for calculating the potential distribution in the depleted top layer and in the substrate of a buried-channel charge-coupled (BCCD) device. The depletion approximation is used. The experimental verification of the method is done by comparing the results with measured values for the maximum channel potential Φ MAX , the location Y m of that maximum, and the location H of the edge of the p-n depletion layer into the substrate.

Real space transfer noise in buried-channel devices

The noise due to the spilling of hot electrons out of potential wells and subsequent trapping is calculated. This noise is the real space analogy to the intervalley noise in transfer devices. Our results show that this noise can be important for heterojunction FET's and MOS devices. The Thornber formalism used in our calculation is general and applies for nonstationary cases. Results are given only for the specific case of buried-channel charge-coupled devices because for other devices this type of noise can be derived as a special case.

Comments on "A device model for buried-channel CCD's and MOSFET's with Gaussian impurity profiles

In the above paper, an expression for the silicon-surface potential in the ion-implanted channel region of a depletion MOST includes both the flat-band voltage V FB and the potential difference Δ between the conduction band and the Fermi level. It is shown here that Δ is inherently included in V FB hence, the original expression requires correction.

Multiple buried channel charge-coupled device

Charge storage characteristics of a vertically stacked multiple p- n layer Si structure, under fully depleted condition, are investigated analytically and the feasibility of operating such structure as the multiple buried channel charge-coupled device (MBCCD) is discussed. Fabrication requirements of the device are outlined and the infleunce of parameter variations on its operational characteristics are described.

A technique for suppressing dark current generated by interface states in buried channel CCD imagers

A technique for operating buried channel CCD imagers to achieve very low dark current with no loss in optical sensitivity is described. Using this technique on a 4-phase CCD shift register operated in an imaging mode, the dark current is reduced from 7.0 nA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to 0.60 nA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 295°K.

Planar sealed-channel gallium arsenide Schottky-barrier charge-coupled devices

We report the demonstration of GaAs Schottky-barrier buried-channel charge-coupled devices(SBCCD's) that are unique in three respectS. First, a planar configuration has been achieved by use of a Schottky-barrier channel stop. Secondly, a sealed channel has been provided by an overlapping gate structure achieved with two-level gate metal and dielectric isolation. Finally, charge transfer has been obtained with a two-layer GaAs structure, n-type over p-type, as well as with a single n-type layer on a Cr-doped substrate as employed for all previously reported GaAs SBCCD's. Characterization of charge-transfer behavior has emphasized comparative behavior of the single-and double-layer structures.

Inherent Signal-to-Noise Ratio Limitations of Charge-Coupled Device Pseudonoise Matched Filters

Inherent SNR limitations of CCD pseudonoise matched filters (PNMF) due to fat-zero noise, input circuit noise, thermal dark current, reset noise, and charge-transfer inefficiency are investigted. It is shown that for practicable integrated circuits using buried-channel CCD's, these device limitations will rarely degrade performance enough to compete with the code correlation self-noise.

A 256K-Bit Charge-Coupled Device Memory

This paper describes the design of an experimental 256K-bit serial-access memory using VLSI fabrication technology and low-power dynamic circuits. The memory array chip is implemented with a double polysilicon process and uses charge-coupled devices (CCDs) grouped in 64 blocks of 4K bits each. Operation is typically at a 300-ns-per-bit cycle for both read and write modes, with operating voltages of +8.5, +5.0, and -2.2 volts, and with 310 mW of power dissipation. All inputs and outputs, with the exception of a chip enable and two system clock lines, are TTL-level compatible. The unique design features and the organization of the 256K CCD chip are discussed; the array organization, the chip layout, the peripheral circuitry, and the buried-channel CCD device design are described; and test results obtained on experimental hardware are presented.

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.

(Invited) The Buried Channel CCD: an Inherently Reliable Technology

This paper discusses the reliability analysis of N-BCCD technology which was performed at our laboratories. In order to obtain a complete reliability profile of N-BCCD devices, tests were conducted at the test die level, finished device level and system level. The analysis shows that N-BCCD devices are more immune to oxide related failures compared to RAMS due to the reduced magnitude and negative electric field. Operating life test results taken on our 64 K-bit CCD memory (F464) indicate excellent integrity to oxide related failure modes in the memory array. An introduction and future outlook discussion is given to provide the reader with a perspective on this technology.

A New Technique for Hardening CCD Imagers by Suppression of Interface State Generation

A new technique has recently been developed to suppress dark current generation by interface states in buried channel CCD imagers by a change in the operating biases of the CCD during the integration cycle. In this work, this technique is successfully applied to suppressing interface state generated dark current in two irradiated CCDs. A dark current of only 1.3 nA/cm2 at 1 Mrad dose has been obtained on a CCD fabricated with radiation hardened oxides using this technique, compared to 360 nA/cm2 in the normal mode of operation. Experimental data on the irradiated CCDs show an excellent correlation between dark current generated by interface states in the normal mode of operation and the density of interface states measured using the periodic pulse technique.

A device model for buried-channel CCD's and MOSFET's with Gaussian impurity profiles

Analytical forms are developed for the buried-channel CCD and its counterpart the buried-channel MOSFET having Gaussian impurity charge profiles. The results are able to describe all important potentials, charges, distances, and currents in terms of the profile structural parameters. The model will be quite useful in the design of buried-channel circuits for VLSI applications where it is expected that highly nonlinear profiles will be obtained by the use of very shallow ion implants and minimal high-temperature processing.

Evaluation Of A Schottky Infrared Charge-Coupled Device (IRCCD) Staring Mosaic Focal Plane

We describe the operation and performance of two Schottky infrared charge-coupled device (IRCCD) staring sensors. Both sensors are monolithic and are fabricated from conventional integrated circuit grade silicon. The devices include a 256 element linear array and a 25 x 50 element area array of PtSi Schottky photodiodes which are sensitive from 1.1 to 4.6 pm. The 1250 element mosaic incorporates an interline transfer architecture. Signal readout for both devices is via a 4-phase buried channel charge-coupled device network and an on-chip amplifier. The focal plane may be operated between 20°K and 100°K; optimum performance is observed between 50°K and 90°K. We present examples of human thermal imaging against ambient backgrounds as well as photoresponse, thermal transfer, and resolution characteristics. Measured results are compared to theoretical predictions of performance and future developments for this class of sensor are projected.

Determination of buried channel parameters from IV and CV measurements

A simple, direct method is described for the extraction of the minimum carrier potential vs charge packet size in a buried channel CCD. Also obtainable from this technique is a direct measurement of the location of the top of the charge packet with respect to the silicon surface. Close correlation is found between the results obtained from this technique and the predictions of the step junction depletion layer approximation.

Uniphase buried-channel charge-coupled devices

The Uniphase operation of buried-channel CCDs with a single electrode system is described and practical structures are proposed. A stepped-oxide approach using strongly doped/thin-lightly doped/thick regions for the buried layer appears to be best suited for building a uniphase bulk-channel CCD with available technology.

Characteristics of the overlaid charge-coupled device

A novel charge-coupled device structure (the overlaid CCD) is described. It operates by transferring charge packets on two distinct levels which are overlaid in the semiconductor bulk. This bulk-integrated device has an increased density per unit area and a reduced driving power consumption per bit compared to conventional buried-channel CCD's still enjoying bulk-channel operation. Furthermore, the overlaid CCD can be employed to perform certain operations that could otherwise be performed only at greater expense. The price to be paid is a smaller charge-carrying capacity of the deeper laying transfer level. The operational characteristics of the overlaid CCD are investigated by means of analytic, as well as two-dimensional numerical calculations. Emphasis is laid upon assessing the distinguishing features of the device and evaluating the relative influences of the design parameters on the operational performances.

Enhanced capacity CCD

This paper introduces a method for enhancing the charge capacity and lowering the leakage current in CCD's. The two-phase coplanar electrode structure is chosen as a vehicle for demonstrating the concept. The charge capacity enhancement is achieved by a combination of p-type and n-type implantations. This method of charge capacity enhancement relies on the increase of depletion capacitance in the storage well region of the CCD, as contrasted with other methods which increase the surface potential swing. A charge capacity analysis is undertaken and design constraints to provide maximum charge capacity are described. Results of measurements on the first test structure show 25-50-percent increase in charge capacity for buried-channel CCD's and 66-166-percent increase in charge capacity for surface-channel CCD's. A 2X-8X reduction in leakage current has been observed in these CCD's. The increased capacity and decreased leakage current should result in improved performance of CCD's in memory, signal processing, and imaging applications.

WA-A4 a device model for an ion-implanted buried channel MOSFET and buried-channel CCD

WA-A4 a device model for an ion-implanted buried channel MOSFET and buried-channel CCD

A block organized 64-kbit CCD memory

Describes the design and performance of a cost effective 64K CCD memory. The memory is organized 65536/spl times/1 in 16 randomly accessible serial-parallel-serial (SOS) blocks of 4096 bits. The memory operates over a frequency range of 1 to 5 MHz and has an average latency of 410 /spl mu/s at 5 MHz. A chip size of 4.4 mm/spl times/5.8 mm (175 mil/spl times/228 mil) is achieved by interlacing the data and using the electrode per bit approach within the SPS blocks. The chip geometry permits the device to be packaged in conventional 300-mil 16-pin package offering high board density. The typical power dissipation is 220 mW L<3.5 /spl mu/W/bit) in the active mode at 5 MHz and 40 mW (<1/spl mu/W/bit) in the standby recirculate mode at 1 MHz. The device is processed with Isoplanar two-polysilicon gate n-channel technology employing buried-channel CCD structures.