Abstract
A simple, direct method is described for the extraction of the minimum carrier potential vs charge packet size in a buried channel CCD. Also obtainable from this technique is a direct measurement of the location of the top of the charge packet with respect to the silicon surface. Close correlation is found between the results obtained from this technique and the predictions of the step junction depletion layer approximation.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
