Built-in Self-test Design Research Articles

SPI Master Slave Communication

The serial-peripheral interface (SPI) protocol also called asynchronous serial interface specification is used for communication between single master and single/multiple slaves. With the increase in number of slaves causing high complexity of circuit creates a demand in self-test ability feature for SPI module in order to test for fault free circuits. Built-In-Self-Test (BIST) in the answer for self-test in circuits as well as it helps in reduction of maintenance and testing cost. Design of BIST embedded SPI module with single master and single slave configuration has been introduced in these paper, Here 8-bit is transferred across the module, Where the Circuit under Test (CUT) is being Self-Tested with BIST feature for its correctness. This SPI module is designed using Verilog hardware description language(HDL) using EDA playground platform for application like applications specific integrated circuit (ASIC) or system on chip (SOC). SPI stands for the Serial Peripheral Interface. It is a serial communication protocol that is used to connect low-speed devices. It was developed by Motorola in the mid-1980 for inter-chip communication. It is commonly used for communication with flash memory, sensors, real-time clock (RTC), analog-to-digital converters, and more. It is a full-duplex synchronous serial communication, which means that data can be simultaneously transmitted from both directions. The main advantage of the SPI is to transfer the data without any interruption. Many bits can be sent or received at a time in this protocol. In this protocol, devices are communicated in the master-slave relationship. The master device controls the slave device, and the slave device takes the instruction from the master device. The simplest configuration of the Serial Peripheral Interface (SPI) is a combination of a single slave and a single master. But, one master device can control multiple slave devices

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.

An area efficient, high-frequency digital built-in self-test for analogue to digital converter

ABSTRACTA design of the digital built-in self-test (BIST) for an analogue to digital converter (ADC) is presented in this paper with the high-level description of static characteristics. The static characteristics of an ADC have modelled mathematically to develop the building blocks of the BIST. The design of digital BIST is focused on extended fault coverage, the best trade-off in area overhead, improvement in operating frequency and a reduction in power consumption. Proposed testing schemes are implemented using hardware description language and tested in ISE project navigator. The practical results of proposed digital BISTs are compared with the existing on-chip BIST circuits for performance analysis. Final uncertainty of the ADC output has been analysed using proposed testing schemes to detect the static errors. The simulator verifies the uncertainty of the data conversion from the static parameters computed by the BIST.

An Efficient Ic On chip Test Framework To Embed Tsv Testing In Memory Bist Using Dynamic Technique

An end-to-end design of a built-in self-test (BIST) infrastructure for 3D-stacked ICs that facilitate the use of BIST at multiple stages of 3D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both pre-bond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. It results on synthetic stacks assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. It also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.

Detection of Stuck Open and Short Fault in SRAM Based System

A novel scan-based Built-In Self-Test (BIST) architecture is designed with Low-Power (LP) for weighted pseudorandom test pattern generation (WPTPG) and reseeding, which is easy for the pseudorandom testing and deterministic BIST. The pseudorandom testing stage is designed by disabling a section of scan chains and in the deterministic BIST stage, the design-for-testability architecture is reorganize slightly while the linear-feedback shift register is kept short. The proposed technique of a BIST design for fault detection and fault diagnosis of Static-RAM (SRAM) based Field Programmable Gate Array (FPGAs) can detect the interconnect resources in the Configurable Logic Blocks (CLBs). The test pattern generator and output response analyzer are configured by CLBs in FPGAs. The testing procedure undergoes three major test blocks. They are Test Pattern Generator (TPG), Output Response Analyzer (ORA) and Block Under Test (BUT) in each test block. The stuck open and short faults are detected using SRAM based FPGA are observed in this paper.

A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit

ABSTRACT Built-in self-test (BIST) mechanism has been a very important approach for testing embedded memory's function and performance. In this paper, a high-speed BIST design for embedded static random access memory (SRAM) and one-port register file (RF) IPs testing was presented. With the purpose of achieving high-speed requirement, the pipe-line strategy is adopted in BIST circuit. Four SRAM instances and four one-port RF instances with the BIST circuit are integrated in a test chip. And the test chip has been fabricated in 28 nm low-leakage logical process. The final silicon data indicated that the proposed implementation is efficient and reliable for memory testing. Furthermore, the test result also show that the yield of memory instances with BIST circuits in the test chip reached up to nearly 100%.

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM

Mobile Wide-I/O DRAMs are used in smartphones, tablets, handheld gaming consoles and other mobile devices. The main benefit of the Wide-I/O DRAM over its predecessors (such as LPDDRx DRAMs) is that it offers more bandwidth at lower power. In this paper, we propose a Wide-I/O DRAM built-in self-test design, named WIO-BIST including the local BIST (LO-BIST), global BIST (GL-BIST) and test interface structures, to support the fault detection in memory-die channels and TSVs. It should be noted that, a TSV test scheme is presented embedding the test procedure of TSVs into the memory-die channel test processes to significantly save the test time of TSVs. A logic die and 4 memory-dies stacking configuration is used to act as a dedicated circuit to demonstrate the feasibility of the proposed WIO-BIST design. Experimental results and comparisons show that the proposed WIO-BIST design has good performance in test time reduction with tiny extra area overhead penalty.

A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs

We present an end-to-end design of a built-in self-test (BIST) and BIST-based diagnosis infrastructure for 3-D-stacked integrated circuits (ICs) that facilitates the use of BIST at multiple stages of 3-D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both prebond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. A framework for fault diagnosis using the BIST infrastructure for 3-D-stacked ICs is also proposed. We present results on synthetic stacks created from ITC’99 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. We also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.

Design of BIST using Self-Checking Circuits for Multipliers

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

It is becoming common to implement header (footer) power switches in low-power system-on-chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built-in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic-high, the tested switches are fault-free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm 2 . The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.

Reconfiguration Schemes Of SC Biquad Filters For Oscillation Based Test

Transformation rules for oscillation based test for different types of switched-capacitor (SC) biquad filter stages based on Fleischer-Laker biquad SC structure are proposed. In our earlier work, a solution for all-pass SC biquads has been reported. In this paper we generalize the approach to other classes of SC filter biquads. Theoretical background of the proposed approach is described and a set of practical design-for-test rules for each of the addressed SC structure is provided. Proposed oscillation based test structures can be included into a built-in self-test design with minimum hardware overhead. DOI: http://dx.doi.org/10.5755/j01.itc.42.1.1695

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

Experimental Results of Testing a BIST Σ–Δ ADC on the HOY Wireless Test Platform

High pin count packaging and 3D IC technology make testing such advanced ICs more and more difficult and expensive. The HOY wireless test platform provides an alternative and cost-effective test solution to address the poor accessibility and high test cost issues. The key idea is implementing a low-cost and short-distance wireless transceiver on chip so that all test instructions and data can be transmitted without physical access. Due to the limited wireless bandwidth, all modules in the device under test (DUT) are preferred to have some built-in self-test (BIST) features. Prior works successfully demonstrated that DUTs with memory and digital circuits can be tested on the low-cost wireless test platform. However, there is no example to show if it is also possible to test the DUT embedded with analog circuits on the HOY test platform. This paper demonstrates the first system-level integration including hardware and software for testing a fully-integrated BIST ADC on the HOY wireless test platform. The DUT chip fabricated in 0.18-μm CMOS consists of a second-order Σ–Δ ADC under test (AUT) and the BIST circuitry. The AUT design employs the decorrelating design-for-digital-testability (D3T) scheme to make itself digitally testable. The BIST design is based on the modified controlled sine wave fitting (CSWF) method. The required BIST circuits are purely digital and as small as 9.9k gates. The gate count of the HOY test wrapper is less than 1k. Experimental results obtained by the HOY wireless test platform show that the AUT achieves a dynamic range of 85.1 dB and a peak SNDR of 78.6 dB. The wireless test results show good agreement with those acquired by conventional analog tests.

A New Architecture of Test Response Analyzer Based on the Berlekamp–Massey Algorithm for BIST

Lately, built-in self-test (BIST) has been of great importance in the manufacture of very large scale integration (VLSI) circuits. Most BIST schemes compress the test response into a compact signature using space and/or time compaction. A fundamental problem associated with response compaction is error masking or aliasing. In this paper, an alternative zero-aliasing test response evaluation scheme for BIST is presented. The main conceptual ingredient utilized to build the proposed scheme is the application of the Berlekamp-Massey algorithm (BMA). The BMA provides a general solution for synthesizing the shortest linear feedback shift register (LFSR) capable of generating a given finite sequence. Basically, on the BIST design stage and considering the fault-free test response sequence, the BMA is used to synthesize an LFSR capable of generating this sequence in an economical way. The BIST testing stage consists in comparing the obtained test response sequence of the circuit under test (CUT) with the fault-free test response sequence generated by the LFSR previously designed. This way, a testing of the CUT can be made. It is observed that there is no aliasing using the proposed scheme. The key to make this scheme attractive is to keep the LFSR length as small as possible. Based on it, two derived schemes, called Simple-LFSR and Multi-LFSR, are shown to try to solve this problem. Experimental results are shown for some ISCAS85 benchmarks.

A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.

Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs

This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

A Fully Integrated Built-In Self-Test $\Sigma{-}\Delta$ ADC Based on the Modified Controlled Sine-Wave Fitting Procedure

This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Σ-Δ modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Σ-Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.

Complex Oscillation-Based Test and Its Application to Analog Filters

Testing is a critical factor for modern large-scale mixed-mode circuits. Strategies for mitigating test cost and duration include moving significant parts of the test hardware on-chip. This paper presents a novel low-overhead approach for design for test and built-in self-test of analog and mixed-mode blocks, derived from the oscillation-based test framework. The latter is enhanced by the use of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">complex</i> oscillation regimes, improving fault coverage and enabling forms of parametric or specification-based testing. This technique, initially proposed targeting large subsystems such as A/D converters, is here illustrated at a much finer granularity, considering its application to analog-filter stages, and also proving its suitability to backfit existing designs. The simple case of a switched-capacitor second-order bandpass stage is used for illustration discussing how deviations from nominal gain, central frequency, and quality factor can be detected from measurements not requiring A/D stages. A sample design is validated by simulations run at the layout level, including Monte Carlo analysis and simulations based on random fault injections.

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA

This paper presents a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM)-based field-programmable gate arrays (FPGAs). The proposed FPGA BIST structure can test both the interconnect resources [wire channels and programmable switches (PSs)] and lookup tables (LUTs) in the configurable logic blocks (CLBs). The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults in LUTs. The applications on XC4000-series FPGAs show that 100% fault coverage of the proposed FPGA BIST structure can be obtained. Additionally, the test results reveal that good performance in fault detection and fault diagnosis on both interconnect resources and CLBs can be achieved at levels similar to those required in previous works.