Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM

Abstract

Mobile Wide-I/O DRAMs are used in smartphones, tablets, handheld gaming consoles and other mobile devices. The main benefit of the Wide-I/O DRAM over its predecessors (such as LPDDRx DRAMs) is that it offers more bandwidth at lower power. In this paper, we propose a Wide-I/O DRAM built-in self-test design, named WIO-BIST including the local BIST (LO-BIST), global BIST (GL-BIST) and test interface structures, to support the fault detection in memory-die channels and TSVs. It should be noted that, a TSV test scheme is presented embedding the test procedure of TSVs into the memory-die channel test processes to significantly save the test time of TSVs. A logic die and 4 memory-dies stacking configuration is used to act as a dedicated circuit to demonstrate the feasibility of the proposed WIO-BIST design. Experimental results and comparisons show that the proposed WIO-BIST design has good performance in test time reduction with tiny extra area overhead penalty.