Abstract
This paper presents a test architecture optimization and test scheduling strategy for TSV based 3D-Stacked ICs (SICs). A test scheduling heuristic, that can fit in both session-based and session-less test environments, has been used to select the test concurrency between the dies of the stack. The proposed method minimizes the overall test time of the stack, without violating the system level resource and TSV limits. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation of individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of SIC. Experimental results show that upto 51% reduction in test time can be achieved using our strategy, over the existing techniques.
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