A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit

Abstract

ABSTRACT Built-in self-test (BIST) mechanism has been a very important approach for testing embedded memory's function and performance. In this paper, a high-speed BIST design for embedded static random access memory (SRAM) and one-port register file (RF) IPs testing was presented. With the purpose of achieving high-speed requirement, the pipe-line strategy is adopted in BIST circuit. Four SRAM instances and four one-port RF instances with the BIST circuit are integrated in a test chip. And the test chip has been fabricated in 28 nm low-leakage logical process. The final silicon data indicated that the proposed implementation is efficient and reliable for memory testing. Furthermore, the test result also show that the yield of memory instances with BIST circuits in the test chip reached up to nearly 100%.