A Jitter Characterizing BIST with Pulse-Amplifying Technique

Abstract

A built-in self-test (BIST) circuit for jitter measurement is proposed. The BIST circuit contains an improved cyclic time-to-digital converter (TDC) to achieve 6-ps resolution, and a pulse amplifier (PA) in front of the cyclic TDC to equivalently enhance timing resolution to 0.6 ps. The quantity of jitter is derived by analyzing the digital output codes of the BIST circuit. The input frequency range of the signal-under-test (SUT) is from 200 MHz to 2 GHz for 0.6-ps timing resolution, and from 100 Hz to 2 GHz for 6-ps timing resolution. In addition to the wide input frequency range and fine resolution, the proposed BIST reduces testing time maximally by 95 % in comparison with the conventional BIST circuit based on component-invariant vernier delay line TDC. The presented BIST circuit occupies 0.6 × 0.336 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.18-um CMOS process.