An area efficient, high-frequency digital built-in self-test for analogue to digital converter

Abstract

ABSTRACTA design of the digital built-in self-test (BIST) for an analogue to digital converter (ADC) is presented in this paper with the high-level description of static characteristics. The static characteristics of an ADC have modelled mathematically to develop the building blocks of the BIST. The design of digital BIST is focused on extended fault coverage, the best trade-off in area overhead, improvement in operating frequency and a reduction in power consumption. Proposed testing schemes are implemented using hardware description language and tested in ISE project navigator. The practical results of proposed digital BISTs are compared with the existing on-chip BIST circuits for performance analysis. Final uncertainty of the ADC output has been analysed using proposed testing schemes to detect the static errors. The simulator verifies the uncertainty of the data conversion from the static parameters computed by the BIST.