A New Architecture of Test Response Analyzer Based on the Berlekamp–Massey Algorithm for BIST

Abstract

Lately, built-in self-test (BIST) has been of great importance in the manufacture of very large scale integration (VLSI) circuits. Most BIST schemes compress the test response into a compact signature using space and/or time compaction. A fundamental problem associated with response compaction is error masking or aliasing. In this paper, an alternative zero-aliasing test response evaluation scheme for BIST is presented. The main conceptual ingredient utilized to build the proposed scheme is the application of the Berlekamp-Massey algorithm (BMA). The BMA provides a general solution for synthesizing the shortest linear feedback shift register (LFSR) capable of generating a given finite sequence. Basically, on the BIST design stage and considering the fault-free test response sequence, the BMA is used to synthesize an LFSR capable of generating this sequence in an economical way. The BIST testing stage consists in comparing the obtained test response sequence of the circuit under test (CUT) with the fault-free test response sequence generated by the LFSR previously designed. This way, a testing of the CUT can be made. It is observed that there is no aliasing using the proposed scheme. The key to make this scheme attractive is to keep the LFSR length as small as possible. Based on it, two derived schemes, called Simple-LFSR and Multi-LFSR, are shown to try to solve this problem. Experimental results are shown for some ISCAS85 benchmarks.