Built-in Self-test Design Research Articles

A Built-in-Self-Test Σ-Δ ADC Prototype

This paper presents a built-in-self-test (BIST) Σ-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard − 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper describes a new adaptive built-in self-test (BIST) technique for detecting stuck-open faults in a CMOS complex cell. A test pattern generator (TPG) that adaptively generates a sequence of single-input-change test pairs based on the past responses of the circuit under test (CUT) is designed. Conventional TPGs produce a predefined sequence of test vectors. The novelty of the proposed approach lies in the fact that the test sequence (TS) generated by the TPG depends on the actual error produced by the CUT during testing. The BIST design is universal, i.e., independent of the structure or functionality of the CUT, and depends only on the number of inputs to the CUT. The length of the TS <formula formulatype="inline"><tex>$(\vert \hbox{TS}\vert)$</tex></formula> also depends on the error behavior; hence, it significantly reduces the average test application time. For an <formula formulatype="inline"><tex>$n$</tex></formula>-input CUT, it is shown that <formula formulatype="inline"> <tex>$4 \leq \vert \hbox{TS} \vert \leq 2n \cdot 2^{n}$</tex></formula>. The design of the response analyzer is also simple. Barring a few exceptions, any irredundant multiple stuck-open faults, including those simultaneously occurring in both the <formula formulatype="inline"><tex>$n$</tex></formula>- and <formula formulatype="inline"><tex> $p$</tex></formula>- parts of a complex cell, are guaranteed to be detected using the proposed BIST scheme. </para>

Column-matching based mixed-mode test pattern generator design technique for BIST

A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algorithm to synthesize the test pattern generator. In principle, we synthesize a combinational block – the decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. The column-matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead. Our BIST exploits mixed-mode testing principles. The BIST execution is divided into two disjoint phases – the pseudorandom phase and the deterministic phase. This enables to reach high fault coverage in a short test time and with a low area overhead. The choice of the lengths of the two phases directly influences the test time, BIST design time and BIST area overhead. A big effort has been put to a capability of trading-off the design criteria. The method allows for scaling the test time, BIST area overhead, BIST design time, etc. The time complexity of the algorithm is studied and experimentally evaluated.

Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test

This paper addresses the optimization of very large scale integration testing systems, specifically the structure design and optimization of a built-in self-test (BIST) design based on two-dimensional (2D) linear feedback shift registers (LFSRs). The 2D LFSRs can generate both precomputed test patterns (for detecting random-pattern-resistant faults) and random patterns (for detecting random-pattern-detectable faults) and have the advantages of high fault coverage and at-speed testing. To guarantee solutions, it is necessary and desirable to generate subsequences of the precomputed test patterns through the 2D LFSRs, where these subsequences retain the order of the test patterns, particularly for testing sequential circuits. For the design and optimization of the 2D LFSRs, the following two problems need to be solved: 1) the good partitioning of the precomputed test patterns into disjoint subsequences in order to achieve a minimal hardware and 2) the structure design and optimization of the 2D LFSRs to generate the test patterns in each partitioned subsequence. The optimization of the 2D LFSRs is modeled as an integer program (a logic optimization model) that determines the coefficients of the recursive Boolean equations that govern the generation of the test patterns. For a sequence of the test patterns, this model finds the minimal-hardware implementation of the 2D LFSRs. This logic optimization model can be applied to both test-per-scan (serial BIST) and test-per-clock (parallel BIST). This paper presents how this model is embedded in a heuristic framework to partition the test patterns into subsequences from the configurable 2D LFSRs. The testing hardware is small as the configurable architecture allows the tester to incrementally generate the precomputed test patterns by modification to the feedback of the 2D LFSRs. Results of benchmark circuits show that significant hardware reduction and higher fault coverage are achieved. The resulting multisequence test generator is a regular structure and is easy to implement. The logic optimization model is applicable to both completely and partially specified test patterns and can be adopted for other LFSR-based structure design and optimization.

Functional-oriented mask-based built-in self-test

Built-in self-test (BIST) is a key design-for-testability technique for digital systems in nanometre technologies. BIST design is usually quite intrusive. In fact, BIST-per-scan or BIST-per-clock schemes require the replacement of all circuit registers by modified flip-flops or registers with extra functionality, which may lead to unacceptable area overhead and, especially, performance degradation. However, for some applications, system performance cannot be compromised by BIST insertion. Moreover, many applications have multiple clock domains and need to be self-tested at speed, during product lifetime. The functional-oriented mask-based BIST is proposed as a minimum impact BIST design methodology. The proposed approach uses testability metrics and circuit functionality to iteratively obtain a BIST solution with the required fault coverage (FC). It can be implemented in multiple clock domain designs and lead to short BIST sessions and a limited impact on system performance. A real world case study, for which system performance is critical, is used to demonstrate that high FC values in a sequential circuit can be achieved, operating at-speed with multiple clock signals, with minimum performance degradation and with lower hardware overhead than the one obtained with a BIST-per-scan solution. The case study is a two-clock domain Sync core for the Synchronisation and Link Board of electromagnetic calorimeter and hadron calorimeter detectors of the CERN compact Muon solenoid experiment.

Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper proposes a new IDD sensor for built-in self-test (BIST) applications for digital, analog, and mixed- signal circuits. This novel, wide-band, nonintrusive, process and temperature-stable IDD sensor operates up to 230 MHz, which is 2.3<formula formulatype="inline"><tex>$\times$</tex></formula> faster than previously proposed designs, and occupies 78.3% less area than another competing design. A BIST utilizing this novel IDD sensor is created and tested on numerous digital circuits, as well as on an op-amp and a mixer, achieving up to 90% fault coverage, while maintaining the performance of the circuit- under-test. The experiments were implemented in 0.18-<formula formulatype="inline"><tex>$\mu$</tex></formula>m TSMC CMOS mixed-signal technology. </para>

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Low power dissipation (PD) during testing is emerging as one of the major objectives of a built-in self-test (BIST) designer. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power BIST scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable test pattern generators (TPGs), (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. Results indicate that the total power dissipated, the average power per test vector and the peak PD during testing can be reduced up to 73%, 27% and 36% respectively with respect to earlier schemes, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.

BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

This paper presents a built-in self-test (BIST) scheme for detecting all robustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit. The test pattern generator (TPG) generates all n . 2n single-input-change (SIC) ordered test pairs for an n-input circuit-under-test (CUT) contained in a sequence of length 2n.2n. The proposed design is universal, i.e., independent of the structure and functionality of the CUT. A counter that counts the number of alternate transitions at the output of the CUT, is used as a signature analyzer (SA). The design of TPG and SA is simple and no special design- or synthesis-fortestability techniques and/or additional control lines are needed.

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories

The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are March based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground March algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports March algorithms, including the proposed multibackground one.

Handling the pin overhead problem of DFTs for high-quality and at-speed tests

The pin overhead problem of nonscan design for testability (DFT) and built-in self-test design has been an unsolved problem for a long time. A new algorithm is proposed to connect extra pins of control test points with primary inputs. An economical test point structure is introduced, in which only one gate delay is added to the corresponding functional paths inserted into a control test point. Unlike almost all of the previous nonscan DFT methods which do not handle pin overhead well, this method allows at most three extra pins. Techniques are presented to connect an extra input of a control test point to a primary input in order to avoid conflicts produced by the newly generated reconvergent fanouts. Similar techniques are proposed to connect more than one control input with the same PI. Sufficient experimental results are presented to demonstrate the effectiveness of the method.

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.

BIST Analysis of an Embedded Memory Associated Logic

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed‐forward connections between the data‐path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two‐port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built‐in self‐test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs, but may also be suitable for use with other detection probability tools and simulation tools.

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

Economics modeling of multichip modules testing strategies

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10–20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to non optimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products.

Efficient approaches to low-cost high-fault coverage VLSI BIST designs

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that (BIST and its derivative (BIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead.

Built-in self-test generator design using nonuniform cellular automata model

The paper presents a new test vector generator construction technique for built-in self-test (BIST). The technique is based on the cellular automata model nonuniform cellular automata (NUCA). In NUCA, cell neighbourhoods are not predefined but decided for each cell dynamically by the test vector set. The problem of finding the minimum NUCA topology that can generate a given precomputed test vector sequence is worked on and reduced to independent set-covering problems. Also, a polynomial time algorithm that decides on a small, but not minimal, cellular topology is introduced. Simulations using benchmark circuits showed that the hardware component cost of a test vector generator based on the NUCA model is considerably less than the cost of a single programmable logic array (PLA) approach.

Built-in self-test design of current-mode algorithmic analog-to-digital converters

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques has been employed in analog-to-digital (A/D) converters to eliminate errors caused by offset and low frequency noise, and to cancel the error effect. However, the self-compensating/calibration techniques may no longer work properly in the presence of faulty switching elements. This paper presents the fault behaviors and test generation of a current-mode algorithmic A/D converter, where the single stuck-at faults in the switching elements of the converter are assumes. The converter requires only two test currents to achieve a full testability. Due to the simplicity of generating test currents and the expected outputs, a simple built-in self-test (BIST) structure is proposed. Two extra pins for test enable signal and error indicator are needed. Results show that the full self-testability of the BIST structure is achieved with a low pin/hardware overhead, and the use of expensive test equipment is not necessary.