Handling the pin overhead problem of DFTs for high-quality and at-speed tests

Abstract

The pin overhead problem of nonscan design for testability (DFT) and built-in self-test design has been an unsolved problem for a long time. A new algorithm is proposed to connect extra pins of control test points with primary inputs. An economical test point structure is introduced, in which only one gate delay is added to the corresponding functional paths inserted into a control test point. Unlike almost all of the previous nonscan DFT methods which do not handle pin overhead well, this method allows at most three extra pins. Techniques are presented to connect an extra input of a control test point to a primary input in order to avoid conflicts produced by the newly generated reconvergent fanouts. Similar techniques are proposed to connect more than one control input with the same PI. Sufficient experimental results are presented to demonstrate the effectiveness of the method.