High Speed Built in Self-Test via Pattern Generation

Abstract

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labelling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. Dividing Circuits, Integrated Circuit Testing, Integrated Circuit Design, Design For Testability, Digital Arithmetic, Built In Self-Test, Graph Theory, Built In Self-Test Design, High Speed Carry Free Dividers, C Testable Circuits, Graph Labelling, Test Patterns, Control Signals, 64 Bit, Built In Self-Test, Circuit Testing, Automatic Testing, Test Pattern Generators, Hardware, Signal Generators, Test Equipment, Costs, Controllability, Observability, In Spartan3E FPGA device family, computation of 8-bit circular convolution using Modified Karatsuba Algorithm.