Abstract
A low peak power consumption built-in self-test (BIST) design based on genetic algorithm (GA), which is denoted by GAITPG, has been proposed in our previous study. This paper presents an improved performance of GAITPG, which also aims at the reduction of the changes between successive test patterns. (m-1) vectors were inserted between two successive n-bit pseudorandom test patterns generated by the original linear feedback shifted register (LFSR), while m and the element of groups were optimized by GA. Experimental results based on ISCAS'85 benchmark circuits show that the test pattern generator (TPG) with low power consumption proposed in this paper is efficient, without losing stuck-at fault coverage. Also, a comparison of reduction of power consumption between GAITPG and other scheme (such as inserted TPG (ITPG)) was reported.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
