Abstract
This paper presents a built-in self-test (BIST) design of a high-speed C-testable divider. The divider can be fully tested using 72 test patterns irrespective of the circuit size (C-testability). Its test patterns, expected outputs, and control signals can be represented by sets of labels using a graph labeling technique. Due to the simplicity of the repetitive label sets, test patterns can be easily generated inside chips and responses to test patterns need not to be stored. Thus, use of expensive test equipment is not necessary. Results show that, for the BIST design of a 64-bit C-testable divider, its hardware overhead is less than 5%.
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