Breakdown Voltage BVCEO Research Articles

Transferred-substrate InP/InGaAs/InP double heterojunctionbipolar transistors with f max = 425 GHz

InP/InGaAs/InP double heterojunction bipolar transistors (DHBTs) with fmax = 425 GHz and fτ = 141 GHz using transferred-substrate technology are reported. This is the highest reported fmax for a DHBT. The breakdown voltage BVCEO is 8 V at JC = 5 × 104 A/cm2 and the DC current gain β is 43.

Implanted collector profile optimization in a SiGe HBT process

Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f T to be increased without degrading the collector emitter breakdown voltage BV CEO. The fabricated devices demonstrate a highest f T of 60 GHz. Depending on the collector profile BV CEO values between 1.5 and 2 V were obtained.

Current gain control of near infrared c-Si phototransistors

c-Si phototransistors with base junction depth around 4.0 μm with its common emitter DC current gain h FE within 300–1100 had been well controlled by implanting base doping levels from 3×10 14 to 6×10 14 cm −2, which is suitable in any conventional commercial photosensing application. According to the experimental results, the higher the base doses implanted, the lower and more stable is the DC current gain h FE obtained. The higher base implanting doping level results in reproducible and uniform wafers. The common emitter open base breakdown voltage BV CEO ranges from 35 V (for lightly doped base) to 140 V (for heavier doped base) under the test condition of I CEO=100 μA, and the collector–emitter leakage current for base current I B=0. The open emitter breakdown voltage is within 40 V for lightly doped base, ∼220 V for heavier doped base under I CBO=100 μA and I E=0 A. The breakdown mechanism includes punch through and avalanche multiplication.

A low-complexity 62-GHz fT SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget

A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900°C for 10 s as the highest temperature step. A very high current gain of almost 2000 and cut-off frequency of 62 GHz were achieved for a uniform 12% Ge profile. The breakdown voltage BV CEO and forward Early voltage were equal to 2.9 and 6.5 V, respectively.

Simulation of the electrical characteristics of AlGaN/GaN heterojunction bipolar transistors

Heterojunction bipolar transistors fabricated from the III–V nitrides offer improved linearity for high-power and high-frequency amplifiers. We report the results of two-dimensional simulations of the characteristics of AlGaN/GaN heterojunction bipolar transistors (HBTs) using the MEDICI® simulator. The simulated performance of single-heterojunction devices predict that it is possible to realize an amplification coefficient β=1130, an emitter-base turn-on voltage V BCO =3 V , a collector saturation current I Csat =3.5 kA / cm 2 , and a collector breakdown voltage BV CEO =55 V . The simulated frequency response of these devices indicate a maximum cutoff frequency f T =18 GHz .

DC and high-frequency performance of AlGaN/GaN Heterojunction Bipolar Transistors

The DC and high frequency performance of AlGaN/GaN Heterojunction Bipolar Transistors (HBTs) is analyzed using an enhanced drift-diffusion model and GaN/AlGaN material parameters, which were previously verified by modeling experimental device characteristics. The emitter–base diode turn-on voltage is as high as 2.7 V while the collector and base ideality factors are 1.16 and 1.46 respectively. A DC current gain of β=15 is found at a collector current density of 2.5 kA/cm 2 and the gain is maintained at this value up to 4.1 kA/cm 2. The devices show a small offset voltage of 0.5 V. A forward breakdown voltage BV CEO of 70 V is found for designs with collector doping of 5×10 16 cm −3. The current gain varied from 22 to 6 when the base doping was increased from 5×10 17 to 2×10 18 cm −3. At the same time, the maximum oscillation frequency f MAX increased from 3 to 6 GHz. A severe degradation of the current gain, f T, and f MAX was observed for HBT designs with a base thickness wider than 1000 Å. By optimizing the transistor design and bias, an f T of 44 GHz and an f MAX of 24 GHz are predicted. Results of a large-signal analysis are also presented to evaluate the power capability and efficiency of AlGaN/GaN HBTs.

MBE-grown SiGe base HBT with polysilicon-emitter and TiSi 2 base ohmic layer

Using Si SiGe heteroepitaxy grown by solid-sources (SS) molecular beam epitaxy (MBE) on LOCOS-patterned wafers, an n-p-n Si/SiGe/Si heterojunction bipolar transistor (HBT) which is isolated by a polysilicon-filled trench has been fabricated. Unlike other SiGe HBTs using a metallic salicide process, in this proposed device a titanium disilicide (TiSi 2) base electrode layer is formed by deposition and patterning of an amorphous TiSi 2. x ( x = 0–0.9) layer on the SiGe base layer using selective wet etching. In view of a lower thermal budget furnace annealing at 840°C has only been applied for the drive-in and activation of arsenic (As) implanted in the polysilicon-emitter. The Si/Si 0.85Ge 0.15/Si n-p-n HBT with a 1 × 4 μm 2 mask size emitter typically shows a common-emitter current gain of 118, an Early voltage in the range of 150–170 V, a breakdown voltage BV ceo of 7.8 V, a unity current gain frequency f T of 20 GHz, and a maximum oscillation frequency f max of 15 GHz. Considering the theoretical limit of f T vs BV ceo, the performance of our device is near the limit and demonstrates a potential for high frequency analog IC applications.

High-performance InP/InGaAs heterojunction bipolar transistors with highly carbon-doped base grown by chemical beam epitaxy

InP/In0.53Ga0.47As heterojunction bipolar transistors (HBTs) using a highly carbon-doped base are reported. High carbon doping has been achieved by chemical beam epitaxy (CBE). The resulting hole concentration in the carbon-doped base is as high as 7 × 1019/cm3. To our knowledge, this is the highest doping level reported using carbon. HBTs with 20 A spacer layer exhibited nearly ideal I-V characteristics with collector and base current ideality factor of 1.018 and 1.037, respectively. Current gain and breakdown voltage BVCEO were 7 and 6 V, respectively.

Performance tradeoffs in AlInAs/GaInAs single- and double-heterojunction NpN heterojunction bipolar transistors

This article reports on the speed‐power tradeoffs between single‐ and double‐heterojunction AlInAs/GaInAs heterojunction bipolar transitor devices. Single‐heterojunction devices with ft=100 GHz and fmax=112 GHz have been demonstrated with a breakdown voltage BVceo=2.5 V. AlInAs collectors produce higher breakdown voltages, but reduced current gain bandwidth (e.g., ft=30 GHz/BVceo=7.5 V), which results in a limited ft‐BVceo product. Simulations of transient electron transport in the collector confirm that the low saturated velocity of AlInAs leads to long collector transit times. A significant improvement in the ft‐BVceo product can be made by using an InP collector (ft=70 GHz and BVceo=7 V).

Particle-free wafer cleaning and drying technology : H. Mishima, T. Yasui, T. Mizuniwa, M. Abe and T. Ohmi. IEEE Trans. Semicond. Mfg2(3), 69 (1989)

Using SiSiGe heteroepitaxy grown by solid-sources (SS) molecular beam epitaxy (MBE) on LOCOS-patterned wafers, an n-p-n Si/SiGe/Si heterojunction bipolar transistor (HBT) which is isolated by a polysilicon-filled trench has been fabricated. Unlike other SiGe HBTs using a metallic salicide process, in this proposed device a titanium disilicide (TiSi2) base electrode layer is formed by deposition and patterning of an amorphous TiSi2.x (x = 0–0.9) layer on the SiGe base layer using selective wet etching. In view of a lower thermal budget furnace annealing at 840°C has only been applied for the drive-in and activation of arsenic (As) implanted in the polysilicon-emitter. The Si/Si0.85Ge0.15/Si n-p-n HBT with a 1 × 4 μm2 mask size emitter typically shows a common-emitter current gain of 118, an Early voltage in the range of 150–170 V, a breakdown voltage BVceo of 7.8 V, a unity current gain frequency fT of 20 GHz, and a maximum oscillation frequency fmax of 15 GHz. Considering the theoretical limit of fT vs BVceo, the performance of our device is near the limit and demonstrates a potential for high frequency analog IC applications.

A 256 bit 12L RAM with a high‐voltage analog circuit

AbstractRecently, it has become desirable for the analog‐digital LSI to have ROM, PLA, or RAM in addition to the conventional random logic circuits: I2L described in this paper is suitable for these purposes with its capability to be on‐chip with high‐voltage analog circuits. to suppress the circuit area increase which is the largest problem in coexistence with the high‐voltage devices, this RAM has a simplified peripheral circuit by an extensive use of I2L devices. Also, it has a circuit configuration which minimizes the number of device isolation regions. As operating features, it uses the memory cell read‐out transistor in the reverse mode during the signal read‐out in association with the simplification of the circuit configuration. Thus, it is possible to set up the power consumption according to its use. As a result of the fabrication of 256 bit RAM using the process technology for high‐voltage analog circuits (epitaxial layer: 1 ω cm, 10 μm, device‐isolation distance: 20 μm), npn transistor breakdown voltage BVCEO of 22 V, RAM area of 1.7 × 3.4 mm2, minimum access time 600 ns, and minimum write pulsewidth of 440 ns have been obtained.

Emitter-collector breakdown voltage BV ceo versus gain h FE for various n-p-n collector doping levels

The communication presents a set of design curves of collector-emitter breakdown voltage BVceo versus gain hFE for various collector doping levels and thickness for n-p-n transistors. The results include epitaxial layer punch through and radial c-b junction breakdown.

A New Transistor with Improved Safe Operating Area

Gate Associated Transistor (GAT) has been shown to have larger safe operating areas (SOAs) than conventional transistors in both forward and reverse base drive operations. Improvement in SOAs was achieved by the gate shielding effect, which suppressed both current crowding in base layer and avalanche multiplication in collector region. High frequency GATs were fabricated with a maximum oscillating frequency Fmax of 400 MHz, collector-emitter breakdown voltage BVCEO of 240 volts. The output power of 52 W, gain of 20.2 dB, and efficiency of 68% in B class amplifier at the operating frequency of 30 MHz were obtained.