Basic Gates Research Articles

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

All optical logic gates based on nanoplasmonic MIM waveguides

In this paper, we propose and investigate some designs of basic plasmonic logic gates in two dimensional plasmonic waveguides with nanotube metal-insulator-metal waveguides using the numerical method of eigenmode expansion. These gates, including XOR, OR, NOT, and Feynman gate can be realized by changing geometrical parameters properly. Also, by cascading and combining these basic logic gates, any complex logic function can also be obtained providing the highly integrated optical logic circuits. The proposed logic gates have the broadband up to 300 nm and only spend the compact size as much as 2 µm×1.2 µm. Thus, the devices can be applied widely and significantly in optical computing and processing devices.

A Novel Device to Implement Full Set of Three-Input Logic Gates Using a Naphthalene-Based Single-Molecule Field-Effect Transistor

The realization of computational circuits in the nanometer scale leads to a higher speed, lower power consumption, and less occupied area on the chip surface in electronic systems. Two of the most important basic logic gates are three-input exclusive-OR (XOR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) and three-input majority (MAJ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) gates which are the two main functions used in designing computational circuits like full-adder (FA) cells. In this article, a new device (molecular transistor) is presented using the naphthalene molecule. The effects of the input terminal variation of the proposed transistor on its output have been studied. According to the results obtained from the simulation, by applying different voltages to the gate-terminal of the transistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {g}}$ </tex-math></inline-formula> ), the negative differential resistance (NDR) behaviors are observed at different intervals of the source-drain voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {sd}}$ </tex-math></inline-formula> ). Due to the interesting characteristics of the proposed transistor, a full set of three-input basic logic gates is designed and presented. In these gates, a single transistor is utilized and by applying different bias voltages, it can generate different outputs suitable to the intended functions. Besides, an FA cell is designed using the proposed three-input logic gates. The transistor, the gates, and the FA are simulated using nonequilibrium Green’s function (NEGF) and density functional theory (DFT) to verify their functionality.

Design of a new BUS for low power reversible computation

Optimization of device power can be achieved using reversible logic computation and this technique can be applied to a variety of low power applications such as optical computing, nanotechnology, Complementary Metal Oxide Semiconductor (CMOS), Very Large-Scale Integrated Circuits (VLSI) design and many more. Basic and universal gates are the elementary building blocks of digital system. In this paper, a new reversible Basic, Universal and Special (BUS) gate is proposed that is available as a single gate with multiple functionalities as basic (AND, OR & NOT), universal (NAND & NOR) and special gate (EXOR). The proposed BUS gate is implemented on Field Programmable Gate Array (FPGA) and simulated using 180 nm and 90 nm CMOS process technologies. Manchester adder and C17 circuit of ISCAS’85 (International Symposium on Circuits and Systems-1985) benchmark suite using BUS gate are designed and verified using Electronic Design Automation (EDA) tools. There is a power reduction of about 64.41% and 14.06% at 180 nm and 90 nm CMOS process technologies respectively in reversible BUS gate as compared to conventional CMOS-based designs. Thus, this paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems with low power dissipation.

Estimation of Leakage Power and Delay in CMOS Circuits

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

The dual-threshold quantum image segmentation algorithm and its simulation

Various quantum computing simulation platforms have developed rapidly in the last 3 years. However, few quantum image processing algorithms are simulated in these platforms. In this paper, we design a dual-threshold quantum image segmentation algorithm and simulate it in IBM Q Experience platform through Qiskit extension. The NEQR quantum image representation model is firstly optimized and simulated, which is found that the number of the auxiliary qubits will not increase as the image’s size increases. Then, an efficient quantum comparator to realize the comparison of two numbers is designed. And finally, the high parallelism image segmentation algorithm is proposed and simulated. Suppose the size of an image is $${{2}^{n}}\times {{2}^{n}}$$ and the gray-scale scope is [0, $${{2}^{q}}-1$$ ], the time complexity analysis for the quantum image segmentation algorithm shows that the number of basic quantum gate required is proportional to q and will not increase as image’s size increases. Thus, the proposed quantum segmentation algorithm is highly parallelism and has polynomial time complexity. In addition, the simulation part of this paper will provide reference for other quantum image processing algorithms.

Design analysis and applications of all-optical multifunctional logic using a semiconductor optical amplifier-based polarization rotation switch

In this communication, a new semiconductor optical amplifier (SOA)-based module for multi-valued logic units using the cross-polarization modulation effect is proposed and analyzed. The design is simple and compact, consisting of only three SOAs and a few passive optical elements. SOAs have very low switching power (< 1mW), and are very small (< 1 mm) and integrable into modern optical integrated circuits. Being multifunctional, the design is versatile; it can function as a demultiplexer, comparator, half adder, half subtractor, and as basic (OR, AND), universal (NOR, NAND), XOR, and XNOR logic gates. This design follows a tree architecture, operates at very high speed (~ 100Gbit/s), and provides a good Q factor (30 dB or more). The corresponding bit error rate (BER) is very low (~ 10–24). In this work, a relative eye opening as large as 90.4% is calculated. The variations in Q and BER with noise and control power are also investigated.

A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR

In this article, a moving accumulative sign filter (MASF) voter model and a low-power serial voting circuit are proposed for high-speed clock data recovery (CDR). Different from the previously reported parallel voter and moving average majority voter (MV), the proposed design is based on the MASF algorithm and adopts a two-stage voting structure. Only D-flip-flop (DFF) and basic logic gates are used to realize the serial voting function of the four continuous lead/lag/hold decision signals. The proposed MV realizes the signal processing of the four-phase error information without using traditional gain and quantization operations. In addition, by eliminating the redundant output state, the input noise of the digital filter of CDR can be reduced, which could also reduce the power consumption of the subsequent circuits due to less logical flips. As a result, the proposed serial MV can operate at a half baud rate in a high-speed CDR and it can reduce the chip area by removing the demultiplexer unit and the moving average filter. The proposed MV circuit is implemented for a high-speed CDR using a 40-nm CMOS process, which shows a 12-GHz maximum operating speed. The measured power consumption of the whole voter at 10 GHz is only 0.55 mW and the core chip area is 8.6 × 25.4 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design of ternary logic gates and circuits using GNRFETs

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Multioperative reversible gate design with implementation of 1‐bit full adder and subtractor along with energy dissipation analysis

SummaryNanotechnology and very large‐scale integration (VLSI) fabrication have a reflective productivity. The growth of one demands the growth of the other. In nanotechnology, quantum‐dot cellular automata (QCA) secures as the best alternative for replacement of complementary metal‐oxide semiconductor (CMOS) technology for integrated circuit (IC) fabrication. This paper presents an integration of the two domains wherein a novel ultraefficient, multioperative 3 × 3 universal reversible gate, Sadat Farah Vijay (SFV)‐QCA, is proposed and implemented in QCA technology using majority voter approach. SFV‐QCA gate is redesigned and restructured using precise QCA cell interaction for optimization. The basic logic gates are implemented using the proposed SFV‐QCA gate to validate its universality. All the 13 standard Boolean functions are implemented using SFV‐QCA to demonstrate its multioperation nature. One‐bit full adder and subtractor circuits are designed using SFV‐QCA gate and compared with the previous works. The analysis of the SFV‐QCA gate shows that it is ultraefficient and more robust as compared to previous works. Energy dissipation analysis of the designs has also been presented, and the investigation establishes minimum energy dissipation of the designs that confirms ultrahigh efficient designs.

Lithographical Fabrication of Organic Single-Crystal Arrays by Area-Selective Growth and Solvent Vapor Annealing.

Miniaturized organic single-crystal arrays that are addressed by reading-out circuits are crucial for high performance and high-level integration organic electronics. Here, we report a lithography compatible strategy to fabricate organic single-crystal arrays via area-selective growth and solvent vapor annealing (SVA). The organic semiconducting molecules can first selectively grow on photographically patterned drain-source electrodes, forming ordered amorphous aggregates that can further be converted to discrete single-crystal arrays by SVA. This strategy can be applied to self-align the microsized organic single crystals on predesigned locations. With this method, suppression of cross-talk among devices, organic field-effect transistors, and basic logic gate arrays with reading-out electrodes are further demonstrated.

Enzyme-free and DNA-based universal platform for the construction of various logic devices based on graphene oxide and G-quadruplex

In the fields of biocomputing and biomolecular, DNA molecules are applicable to be regarded as data of logical computing platform that uses elaborate logic gates to perform a variety of tasks. Graphene oxide (GO) is a type of novel nanomaterial, which brings new research focus to materials science and biosensors due to its special selectivity and excellent quenching ability. G-quadruplex as a unique DNA structure stimulates the intelligent application of DNA assembly on the strength of its exceptional binding activity. In this paper, we report a universal logic device assisted with GO and G-quadruplex under an enzyme-free condition. Integrated with the quenching ability of GO to the TAMRA (fluorophore, Carboxytetramethylrhodamine) and the enhancement of fluorescence intensity produced by the peculiar binding of G-quadruplex to the NMM (N-methylmesoporphyrin IX), a series of basic binary logic gates (AND. OR. INHIBIT. XOR) have been designed and verified through biological experiments. Given the modularity and programmability of this strategy, two advanced logic gates (half adder and half subtractor) were realized on the basis of the same work platform. The fluorescence signals generated from different input combinations possessed satisfactory results, which provided proof of feasibility. We believe that the proposed universal logical platform that operates at the nanoscale is expected to be utilized for future applications in molecular computing as well as disease diagnosis.

Energy-Efficient Superconductor Bloom Filters for Streaming Data Inspection

Bloom filters can be used in network intrusion detection systems to detect known attack signatures in packet payloads. In this paper we propose and analyze the potential application of superconductor flux quantum technology for streaming data inspection with Bloom filters designed with Reciprocal Quantum Logic (RQL). This paper describes the gate-level design, performance, and energy-efficiency analysis of three superconductor 2 Kbit Bloom filters with 1) the run-time selection of the number of hashes per stream, and 2) different numbers of input streams per Bloom filter. The Bloom filter circuits were designed using a bottom-up approach with manual placing and routing of basic RQL gates. The design complexity is below 97K Josephson junctions. The highest clock frequency reached in the simulation of the circuits is 14.7 GHz. The false positive ra tes of the RQL Bloom filters are in very close agreement with the theoretical expectations of the false positive probability for the filters. For the cryocooling efficiency of 0.1 percent, the RQL Bloom filters demonstrate high energy efficiency in the range of ∼1.5-43.6 pJ/stream/operation at room temperature for stream lengths from 16 to 256 bits. All circuits are designed and simulated for the 248 nm MIT Lincoln Laboratory SFQ5ee fabrication process.

Modeling the Characteristics of SOI CMOS Nanotransistors with an Asymmetric Surrounding Gate

An approach to an end-to-end simulation of the electrophysical characteristics of lowly doped sub-25-nm SOI (silicon-on-insulator) CMOS transistors with an asymmetric surrounding gate composed of two sequentially connected materials with different work functions is considered. The approach consists of the consecutive calculation of the 3D potential distribution in the working region, calculation of the current–voltage characteristics, and calculation of the static and dynamic characteristics for a basic logic gate (an inverter). In the context of the discussed approach, the effect of the ratio between the lengths of the gate regions with different work functions on all the key characteristics of the devices (transistors and logic gates based on them) are analyzed. It is demonstrated that the logic gates can operate efficiently at a supply voltage of 0.8 V, which is a prerequisite for the creation of low-voltage circuit engineering.

Quantum size effect in nanocorrals: From fundamental to potential applications

Conventional silicon-based devices are approaching the scaling limits toward super miniaturization, where the quantum size effect naturally emerges with increasing importance. Exploring the quantum size effect may provide additional functionality and alternative architectures for information processing and computation. Scanning tunneling microscopy/spectroscopy is an ideal tool to explore such an opportunity as it can construct the devices in an atom-by-atom fashion and investigate their morphologies and properties down to the atomic level. Utilizing nanocorrals as examples, the quantum size effect is demonstrated to possess the great capability in guiding the adatom diffusion and the self-assembly, controlling the statistical fluctuation, tuning the Kondo temperature, etc. Besides these fundamentals, it also shows strong potential in logic operations as the basic logic gates are constructed.

Implementation of optical OR and NOR gates using Mach-Zehnder interferometers

The ever increasing growth of data and the need for data transmission emphasizes the requirement of full-optical telecommunication. Therefore, it seems critical to utilize optical integrated circuits, including optical gates, optical dividers, optical converters, etc. In this regard, we introduce a new structure for OR/NOR logical gate. The OR/NOR logical gate is simulated by applying Mach–Zehnder interferometer (MZI) where switching between bar and cross states is implemented by using the electro-optic properties of Lithium Niobate and coupling mode theory. Two different designs for the OR/NOR basic gate are simulated by OptiBPM software. Simulation results show that designed gates implement OR/NOR logical gate completely acceptable. The advantage of these designed gates is that waveguides have smaller length and do not pass above each other; thereby it would be possible to do layering by using fewer layers. Also, results show that output intensity in ‘1’ logic state is more than 95% of input light and in ‘0’ logic state, is less than 5% of the input light.

Smart logic gates constructed by fluorescent-customizable nanoMOFs for diseases monitoring

The molecule computation based on the Boolean logic gates holds great promising in chemical detection, biomarker imaging and disease diagnosis. However, the design of advanced logic gates based on novel nanoplatform of fluorescent-customizable MOFs (metal-organic frameworks) is still in infancy. Herein, whole-visible-spectra fluorescent nanoMOFs are successfully applied to build such a new-generation data processor. Luminescent MOFs (LMOFs) integrated with three functional dyes as DPA, 5-AF and TCPP are synthesized with an in situ one-pot strategy with an ultra-large Stokes shift of 290 nm, in which the dyes undertake multiple roles as modulators, fluorophores, FRET (fluorescence resonance energy transfer) transmitters as well as signal reporters. LMOFs with expected colors can be customized through our established color database, and a model of LMOFs-based barcodes is established to demonstrate the excellent capability of information storage. Through the control of chemical signals as inputs, the elaborated nanoMOFs platform can well implement basic INHIBIT gate, complicated half-adder and a multi-input multi-output (MIMO) logic circuit. Additionally, such MIMO logic circuit is exemplified to assist in the diagnosis of various diseases by taking different disease-related signal species (1O2, ClO− (LOD = 0.3 μM) and Cu2+ (LOD = 2.3 μM)) as input signals, prefiguring the broad application prospects of the developed fluorescent-customizable nanoMOFs in life sciences.

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential lines, supporting the Time Enclosed Logic protocol along with a DPL structure. The security provided by SC-DDPL has been firstly investigated in simulation on some basic logic gates, designed adopting a commercial 40nm CMOS technology. Simulated experiments have highlighted the capability of SC-DDPL gates to guarantee a high-level of security also in presence of extreme capacitive mismatch, exhibiting strongly reduced NED/NSD metrics, as well as a reduction of the FED, compared to a reference RTZ-based WDDL implementation. In order to compare the proposed logic against other state-of-the-art countermeasures we have implemented a 4bit PRESENT crypto-core adopting several logic styles, evaluating different security metrics on a 65nm Intel Cyclone-IV FPGA. Experimental results have confirmed that the SC-DDPL outperforms other gate-level countermeasures in terms of security metrics with a reasonable area and power consumption overhead.

Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing

This paper explores the design and analysis of 20[Formula: see text]nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300[Formula: see text]mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300[Formula: see text]mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20[Formula: see text]nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100[Formula: see text]mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.

Modeling and Simulation Techniques of Amorphous Silicon Thin Film Transistors TFT for Large Area and Flexible Microelectronics

The Thin Film Transistor (TFT) is the key active components of emerging large area and flexible microelectronics (LAFM) which includes a flexible display, robotics skin, sensor &amp; disposable electronics. Different semiconducting or organic conducting materials could be used in the fabrication of TFTs. The material used for the active layer also influences the performance of the TFT uniquely[1]. Silicon based thin film transistors have made possible the development of the active-matrix liquid crystal display within cell-touch technology [2,3,4]. Modern-day simulation software does not support the older SPICE code models, and rather rely on the new drag and drop concepts. The TFT(Thin Film Transistor) Model device wasn't readily available on the LT-Spice Tool which was simulated and the circuit level simulation for basic gates using the TFT was carried out successfully. The model symbol shall be useful for analysis and simulation of the TFT based circuits which require continuous behavioral study and analysis. For a device to be simulated that way, a “.lib” file containing a symbol of the device is necessary. This paper focuses on circuit-level simulation of user-defined device parameters from reported experimental data.