Basic Gates Research Articles

A Logically Reversible Double Feynman Gate with Molecular Engineered Bacteria Arranged in an Artificial Neural Network-Type Architecture.

Reversible logic gates are the key components of reversible computing that map inputs and outputs in a certain one-to-one pattern so that the output signals can reveal the pattern of the input signals. One of the main research foci of reversible computing is the implementation of basic reversible gates by various modalities. Though true thermodynamic reversibility cannot be attained within living cells, the high energy efficiency of biological reactions inspires the implementation of reversible computation in living cells. The implementation of synthetic genetic circuits is mostly based on conventional irreversible computing, and the implementation of logical reversibility in living cells is rare. Here, we constructed a 3-input-3-output synthetic genetic reversible double Feynman logic gate with a population of genetically engineered E. coli cells. Instead of following hierarchical electronic design principles, we adapted the concept of artificial neural networks (ANN) and built a single-layer artificial network-type architecture with five different engineered bacteria, named bactoneurons. We used three extracellular chemicals as input signals and the expression of three fluorescence proteins as the output signals. The cellular devices, which combine the input chemical signals linearly and pass them through a nonlinear activation function and represent specific bactoneurons, were built by designing and creating small synthetic genetic networks inside E. coli. The weights of each of the inputs and biases of individual bactoneurons in the bacterial ANN were adjusted by optimizing the synthetic genetic networks. When arranging the five bactoneurons through an ANN-type architecture, the system generated a double Feynman gate function at the population level. To our knowledge, this is the first reversible double Feynman gate realization with living cells. This work may have significance in development of biocomputer technology, reversible computation, ANN wetware, and synthetic biology.

FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF

Physical unclonable functions (PUFs) have been adopted in many resource-constrained Internet of Things (IoT) applications to provide effective and lightweight solutions for device authentication. However, an attacker can collect challenge–response pairs (CRPs) of a strong PUF, to build a machine learning (ML) model and mimic its behavior, i.e., predicting the responses of unseen challenges with high accuracy. Although several PUFs have been proposed to resist such modeling attacks, they incur high hardware overhead. Developing a PUF primitive with low hardware cost and high resistance to ML attacks is thus a crucial task. In this article, we propose the first response–feedback-based lightweight anti-ML-attack PUF (FLAM-PUF). It is only composed of one arbiter PUF (APUF) and one Galois linear-feedback shift register (LFSR), with some basic logic gates, reducing more than 62% hardware cost compared with the state-of-the-art robust strong PUFs. Specifically, FLAM-PUF leverages a cost-effective feedback loop structure to dynamically control and update the LFSR configuration. FLAM-PUF has two main characteristics: 1) it feeds back a 1-bit response in every cycle to intentionally poison the data of the CRP set for training. To resist ML-based modeling attacks, the 1-bit response can randomly update one coefficient of the feedback polynomial to implant more complex correlations into the model built by attackers and 2) it takes advantage of an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n-$ </tex-math></inline-formula> bit response feedback-controlled reconfigurable Galois LFSR to enlarge the original challenge space of the APUF. Extensive experimental results show that the proposed FLAM-PUF achieves near-optimal uniformity, uniqueness, and reliability. Our scheme works well under standard attack models with public crucial initial information. In particular, the prediction accuracy of modeling attacks against FLAM-PUF is nearly 50% under the four widely used ML algorithms, i.e., support vector machines (SVMs), logistic regression (LR), covariance matrix adaptation evolution strategy (CMA-ES), and deep neural networks (DNNs), indicating excellent resistance against these ML attacks.

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

A novel design of all logic gates in honeycomb photonic crystal and independent of polarization modes (TE/TM) for optical integrated circuit applications

In this paper, a novel microstructure of all the optical logical gates in the 2D honeycomb photonic crystal (2D-HPhC) for optical integrated circuits applications is designed and simulated. In most similar structures, the designs are limited to applications and on the other hand, are limited to the type of optical signal polarization mode (TE or TM). The proposed microstructure is important advantages, including being independent of polarization modes (ie, the proposed logic gate works well with both TM and TE polarization modes), and covers the all-basic logic gates such as AND, OR, NOT, NOR, NAND, XOR, and XNOR. The dimension is very small (suitable for integration), and very low delay time (high speed). The microstructure has three input waveguides (A, B, C) and one output waveguide (Q). The minimum delay time in NAND gate is 0.7 ps. The contrast ratio between the output and input for different gates are 6 dB ∼ 17 dB. The transmission signal rate at best in the XNOR and AND logic gates, and equal to T = 96%. The main function of the microstructure is to use reference input. Reference or controller Input (C) is very important, and by changing the signal phase angle (φ=0° ∼ φ=π°) at this input, all basic logic gates are designed.

Development of ZnO nanoflowers-assisted DNAzyme-based electrochemical platform for invertase and glucose oxidase-dominated biosensing

The investigation on invertase (INV) and glucose oxidase (GOx)-dominated biological process offers a new opportunity for the development of clinical diagnosis and prognostic treatment. Herein, a ZnO nanoflowers (ZnONFs)-assisted DNAzyme-based electrochemical platform for INV- and GOx-dominated biosensing is proposed by the change of pH in microenvironment. In this strategy, INV can usually catalyze the dissolution of sucrose to generate glucose, and glucose is then consumed by GOx to produce H2O2 and gluconic acid, in which ZnONFs can be effectively etched into free Zn2+ ions. Subsequently, the released Zn2+ ions have a shearing action for Zn2+-specific DNAzyme, thus triggering hybridization chain reaction along with the imbedding of methylene blue. The excellent electrochemical signals illustrate the method can be employed well for testing sucrose, INV and GOx with a low detection limit (0.019 μM, 0.047 mU/mL and 0.012 mU/mL, respectively). Finally, a series of basic and advanced logic gates (YES, AND, INHIBIT, and AND-AND-INHIBIT) in the biological process are constructed with different logic inputs, providing a valuable platform for the establishment of advanced molecular devices for bioanalysis and clinical diagnostics.

Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic

Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic

Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator at 1.8v single ended supply voltage and simulations are carried out to indicate the functionality of the proposed full adder circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

A Biosensor Based on Interchain Reactions for the Detection of Acetamiprid and the Construction of Basic Logic Gates OR and AND

An enzyme-free and label-free fluorescent DNA aptasensor was constructed with computer assistance based on thermodynamic deviation driving interchain reactions. In this work, in the presence of target acetamiprid, the released trigger strand C-apt could open hairpin Hp1, which in turn triggered the strand displacement reaction and catalyzed the self-assembly of hairpins Hp1 and Hp2, so that the guanine base rich stem in Hp2 was opened. In the presence of K+ and NMM, the G-rich moiety could form a G-quadruplex and emit strong fluorescence at a specific excitation wavelength. The proposed strategy enables sensitive detection of acetamiprid at concentrations as low as 54.3 pM. Most importantly, computer-assisted analysis of the thermodynamic properties of nucleic acid strands and simulation of the reaction process and conditions of the proposed model before conducting biological experiments theoretically proves this strategy feasible and may simplify subsequent biological experiments. In addition, basic molecular logic gates, including OR and AND, were constructed based on this detection principle, and simulation tests and biological experiments were performed. The final results show that this strategy can not only have some applications in the field of food safety and environmental monitoring, but also provide a certain way for the development of molecular logic computing.

A NISQ Method to Simulate Hermitian Matrix Evolution.

As a universal quantum computer requires millions of error-corrected qubits, one of the current goals is to exploit the power of noisy intermediate-scale quantum (NISQ) devices. Based on a NISQ module–layered circuit, we propose a heuristic protocol to simulate Hermitian matrix evolution, which is widely applied as the core for many quantum algorithms. The two embedded methods, with their own advantages, only require shallow circuits and basic quantum gates. Capable to being deployed in near future quantum devices, we hope it provides an experiment-friendly way, contributing to the exploitation of power of current devices.

A cost-efficient reversible logic gates implementation based on measurable quantum-dot cellular automata

&lt;p class="Abstract"&gt;&lt;span lang="EN-US"&gt;In order to improve the density on a chip, the scaling of CMOS-based devices begins to shrink in accordance with Moore's laws. This scale affects the execution of the CMOS device due to specific limitations, such as energy dissipation and component alignment. Quantum-dot cellular automata (QCA) have been replaced to overcome the inadequacies of CMOS technology. Data loss is a major risk in irreversible digital logic computing. As a result, the market for nano-scale digital operations is expanding, reducing heat dissipation. Reversible logic structures are a strong competitor in the creation of efficient digital systems. A reversing logic gate is an important part of reversible circuit design. The QCA design of basic reversible logic gates is discussed in this study. These gates are built using a new QCA design with XOR gates with two and three inputs. QCADesigner tests simulation performance by simulating the specified reversible logic gate layouts&lt;span&gt;. &lt;/span&gt;The measurement and optimization of design techniques at all stages is required to reduce power, area, and enhance speed. The work describes experimental and analytic approaches for measuring design metrics of reversible logic gates using QCA, such as ancilla input, garbage output, quantum cost, cell count, and area, while accounting for the effects of energy dissipation and circuit complexity. The parameters of reversible gates with modified structures are measured and then compared with the existing designs. The designed F2G, FRG, FG, RUG and UPPG reversible logic gates using QCA technology shows an improvement of 42 %, 23 %, 50 %, 39 % and 68 % in terms of cell count and 31 %, 20 %, 33 %, 20 % and 72 % in terms of area with respect to the best existing designs. The findings illustrate that the proposed architectures outperform previous designs in terms of complexity, size, and clock latency.&lt;/span&gt;&lt;/p&gt;

Composable Gadgets with Reused Fresh Masks

Albeit its many benefits, masking cryptographic hardware designs has proven to be a non-trivial and error-prone task, even for experienced engineers. Masked variants of atomic logic gates, like AND or XOR – commonly referred to as gadgets – aim to facilitate the process of masking large circuits by offering free composition while sustaining the overall design’s security in the d-probing adversary model. A wide variety of research has already been conducted to (i) find formal properties a gadget must fulfill to guarantee composability and (ii) construct gadgets that fulfill these properties, while minimizing overhead requirements. In all existing composition frameworks like NI/SNI/PINI and all corresponding gadget realizations, the security argument relies on the fact that each gadget requires individual fresh randomness. Naturally, this approach leads to very high randomness requirements of the resulting composed circuit. In this work, we present composable gadgets with reused fresh masks (COMAR), allowing the composition of any first-order secure hardware circuit utilizing only 6 fresh masks in total. By construction, our newly presented gadgets render individual fresh randomness unnecessary, while retaining free composition and first-order security in the robust probing model. More precisely, we give an instantiation of gadgets realizing arbitrary XOR and AND gates with an arbitrary number of inputs which can be trivially extended to all basic logic gates. With these, we break the linear dependency between the number of (non-linear) gates in a circuit and the randomness requirements, hence offering the designers the possibility to highly optimize a masked circuit’s randomness requirements while keeping error susceptibility to a minimum.

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks

Side-channel attack (SCA) reveals confidential information by statistically analyzing physical manifestations, which is the serious threat to cryptographic circuits. Various SCA circuit-level countermeasures have been proposed as fundamental solutions to reduce the side-channel vulnerabilities of cryptographic implementations; however, such approaches introduce non-negligible power and area overheads. Among all of the circuit components, flip-flops are the main source of information leakage. This article proposes a three-phase single-rail pulse register (TSPR) based on the three-independent-gate field effect transistor (TIGFET) to achieve all desired properties with improved metrics of area and security. TIGFET-based TSPR consumes a constant power (MCV is 0.25%), has a low delay (12 ps), and employs only 10 TIGFET devices, which is applicable for the low-overhead and high-security cryptographic circuit design compared to the existing flip-flops. In addition, a set of TIGFET-based combinational basic gates are designed to reduce the area occupation and power consumption as much as possible. As a proof of concept, a simplified advanced encryption algorithm (AES), SM4 block cipher algorithm (SM4), and light-weight cryptographic algorithm (PRESENT) are built with the TIGFET-based library. SCA is implemented on the cryptographic implementations to prove its SCA resilience, and the SCA results show that the correct key of cryptographic circuits with TIGFET-based TSPRs is not guessed within 2,000 power traces.

Efficient FPGA architecture to implement non-separable fast Fourier transform for image and video applications

ABSTRACT Fast Fourier Transform (FFT) is widely used in image and video processing applications to convert the respective image or video frames into transform domain that is very helpful to extract the accurate features of that image or video frame for various real-time applications. In this paper, efficient non-separable 8-point FFT architecture (DIT-FFT) is proposed that is implemented on Spartan-6 (xc6slx45-3csg324) FPGA. The proposed architecture consists of Data Format Conversion, Addition, Subtraction, Multiplier Equivalent and D-FF blocks, respectively. The non-separable equations of 8-point DIT-FFT are derived from the respective Butterfly Diagram that is then implemented using basic logic gates, which optimises the hardware utilisations with the help of Complex Conjugate property. The constant multiplications present in the non-separable DIT-FFT equations are implemented through Adders and Shifters presents in Multiplier Equivalent block which further optimises the overall hardware utilisations. Moreover, the Q-format are used to increase the data accuracy of the architecture. The comparison results show that the proposed architecture is better than existing in different prospectives.

Quantum pulse coupled neural network

Artificial neural network has been fully developed in recent years, but as the size of the network grows, the required computing power also grows rapidly. In order to take advantage of the parallel computing of quantum computing to solve the difficulties of large computation in neural network, quantum neural network was proposed. In this paper, based on the pulse coupled neural network (PCNN), quantum pulse coupled neural network (QPCNN) is proposed. In this model, the basic quantum logic gates are utilized to form quantum operation modules, such as quantum full adder, quantum multiplier, and quantum comparator. A quantum image convolution operation applicable to QPCNN is designed employing quantum full adders and neighborhood preparation module. And these modules are employed to complete the operations required for QPCNN. And based on QPCNN, an quantum image segmentation is designed. Meanwhile, the effectiveness of QPCNN is proved by simulation experiments, and the complexity analysis shows that QPCNN has exponential speedup compared with classical PCNN.

Suspicion Distillation Gradient Descent Bit-Flipping Algorithm.

We propose a novel variant of the gradient descent bit-flipping (GDBF) algorithm for decoding low-density parity-check (LDPC) codes over the binary symmetric channel. The new bit-flipping rule is based on the reliability information passed from neighboring nodes in the corresponding Tanner graph. The name SuspicionDistillation reflects the main feature of the algorithm—that in every iteration, we assign a level of suspicion to each variable node about its current bit value. The level of suspicion of a variable node is used to decide whether the corresponding bit will be flipped. In addition, in each iteration, we determine the number of satisfied and unsatisfied checks that connect a suspicious node with other suspicious variable nodes. In this way, in the course of iteration, we “distill” such suspicious bits and flip them. The deterministic nature of the proposed algorithm results in a low-complexity implementation, as the bit-flipping rule can be obtained by modifying the original GDBF rule by using basic logic gates, and the modification is not applied in all decoding iterations. Furthermore, we present a more general framework based on deterministic re-initialization of the decoder input. The performance of the resulting algorithm is analyzed for the codes with various code lengths, and significant performance improvements are observed compared to the state-of-the-art hard-decision-decoding algorithms.

Simulation of Logic Circuit Tests on Android-Based Mobile Devices

In this study, an application that can run on Android and Windows-based mobile devices was developed to allow students attending such classes as Numerical/Digital Electronics, Logic Circuits, Basic Electronics Measurement, and Electronic Systems in Turkey’s Vocation and Technical Education Schools to easily carry out the simulation of logic gates, as well as logic circuit tests performed using logic gates. A 2D-mobile application that runs on both platforms was developed using the C# language on the Unity3D editor. To assess the usability of the mobile application, a one-hour training session was administered in March of the 2017-2018 academic year to two groups of students from a single class in the sixth grade of an Imam Hatip Secondary School affiliated with the Ministry of National Education. Each of the two groups contained 12 students who were assumed to be equivalent and who had no prior knowledge of the subject. The training of the first group began with a lecture on basic logic gates using a blackboard and involved no simulations. In comparison, the second group was given the same lecture and received additional training involving demonstrations of the developed mobile application and its simulations. Following the lectures, a written exam was applied to both groups. An evaluation of the exam results revealed that 83 percent of the students who had been given demonstrations of the mobile application were able to perform the circuit task completely, whereas only 50 percent of the others were able to complete the task. It was concluded that the application was both useful and facilitating for the students, and it was also noted that students who were supported by the mobile application had gained a better grasp of the topic by being able to see and practice the simulations firsthand.

An initial step toward a quantum annealing approach to the discrete logarithm problem

The discrete logarithm problem over a multiplicative group of integer modulo n is the key ingredient in the ElGamal encryption system. This problem has been proven to be tractable in polynomial time on a quantum computer by Shor's algorithm. This algorithm makes use of basic quantum gates, circuits, measurements and it has been experimented in the circuit-gate framework of quantum computing. On the other hand, the adiabatic framework of quantum computing with the quantum annealers such as the D-Wave machine that simulates the adiabatic process has become very popular, showing its potential for making a practical pathway to achieve quantum speedup. Furthermore, much progress has been reported recently on the tractability of the integer factoring problem, which is the other widely-used encryption method, on quantum annealers. In this context, it is important to explore the tractability of the discrete logarithm problem too using quantum annealers. In this work we present a first step made in this direction, by converting the discrete logarithm problem over a multiplicative group into the problem of minimizing a binary quadratic form, a standard problem format acceptable to a quantum annealer. Our formulation was tested for small-scale problem instances using the quantum-classical hybrid platform PyQUBO and we discuss the computational challenges and propose several potential improvements to the formulation.

QCA: A survey and design of logic circuits

Quantum Dot Cellular Automata (QCA) is one of the new technologies beyond CMOS. Among various other technologies, this is considered to be most feasible and viable due to its area and power advantages. In this paper the discussion about the origin and progress of research works is carried out with respect to QCA domain. Starting from the basic gate study and designing of Adders few other functional blocks are also discussed. This paper proposes QCA as it is considered as the upcoming technology after the saturation of CMOS technology. QCA is considered so due to its advantages in area, power and timing requirements. This domain is still under research and has not been carried to large extent. Hence the authors have made an attempt in exploring it through designing and have simulated the proposed designs. the working of the design is proved through the simulation results.

Optimized realization of Quantum Fourier Transform for domestic DCU accelerator

Abstract Quantum Fourier Transform (QFT) is a key part of quantum algorithms such as Shor algorithm, Grover algorithm, and quantum phase estimation algorithm. The “Songshan” supercomputer system adopts the heterogeneous architecture of domestic CPU+DCU. The simulation implementation of the quantum Fourier transform on the “Songshan” supercomputer can promote the research and optimization of related quantum algorithms. Based on the HIP heterogeneous programming model, this paper first maps the phase shift transformation R gate operation of the QFT transformation to the DCU accelerator, and initially constructs the heterogeneous implementation of QFT on the “Songshan” supercomputer; then, the Hadamard gate transformation operation originally implemented on the host side was implemented on the DCU, which greatly reduces the communication overhead caused by the quantum information data transmission between the CPU and the DCU device; finally, the quantum logic gate is analyzed, and based on the operation of the phase shift transformation R gate on the probability amplitude information in the simulation algorithm, an optimization scheme to improve the activity of the DCU thread is proposed. During the experimental verification process, the realized 28-qubit quantum Fourier transform optimization has achieved 13.440 speedup compared with the serially realized QFT simulation on the CPU. The basic quantum gate optimization method based on DCU acceleration equipment in this paper can provide a reference for the efficient simulation of other quantum algorithms on domestic heterogeneous platforms.