Basic Gates Research Articles

Performance Comparison for FinFET Nanoscale Static and Domino Logic Circuits

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16 nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.

Use of Ambipolar Dual-Gate Carbon Nanotube Field-Effect Transistor to Configure Exclusive-OR Gate

As the physical scaling limit of silicon-based integrated circuits is approached, new materials and device structures become necessary. The exclusive-OR (XOR) gate is a basic logic gate performed as a building block for digital adder and encrypted circuits. Here, we suggest that using the ambipolar property of carbon nanotubes and the threshold modulation ability of dual-gate field-effect transistors, an XOR gate can be constructed in only one transistor. For a traditional XOR gate, 4 to 6 transistors are needed, and this low-footprint topology could be employed in the future for hyperscaling and three-dimensional logic and memory transistor integration.

Introduction to Reversible Logic Gates and its Operations

Abstract: Reversible logic is one of the most important issues at the moment and has a wide range of applications, such as low power CMOS, quantum computing, nanotechnol- ogy, cryptography, optical computing, DNA computing, and -digital signal processing (DSP), quantum Dot automata for mobile, communication, computer graphics. It is not possible to detect quantum computing without the implementation of a postponed brain operation. The main objectives of design are logical thinking to reduce quantum costs, circuit depths and the amount of waste disposal. This paper provides basic logical retrospective gates, which in the construction of a highly sophisticated system with retractable circuits as part of the old and unable to perform the most complex operations using quantum computers. Reversible circuits form the basic building block of quantum computers as all quantum functions are reversed. This paper presents data related to older retractable gates found in books and assists research in the design of complex computer circuits using retractable gates. Keywords: Defendable Logic, Portable Gate, Dismissal, Trash, Quantum Cost, Quantum-dot Cellular Automata, Reversible Computing, Reversible ALU, Flip Flop using Reversible Gates, Reversible Adder

Cultural heritage values and underlying spatial characteristics of the Temple of Literature in Vinh Long, Southern Vietnam

PurposeAmong others in South Vietnam, the Temple of Literature in Vinh Long is the only one that has preserved its original form and layout. As such in 1991, the temple was recognized by the Ministry of Culture as a national-level historical and cultural relic. Nevertheless, the temple has been neither studied nor documented to any great depth. Only a few historical descriptions for local tour guidebooks and photo catalogs exist. Therefore this paper aims to initially record heritage values, spatial characteristics and the process of major changes, while documenting the current state of the temple structure and carrying out on-site inspections to survey the buildings.Design/methodology/approachThis paper outlines the collection of survey data through field survey and provides an overview of the existing significant heritage factors of the Temple of Literature in Vinh Long by comparative examination in relation to other surviving temples and analyzing its unique spatial characteristics and indigenous cultural decorations in detail.FindingsAlthough the layout of the temples was influenced by the Chinese Confucius's principles and the notion of Feng Shui, it is evident from the study that the design of the temple has many architectural elements that reveal Vietnam's unique culture and local features. In particular, the Temple of Literature in Vinh Long was a symbol of feudal education, symbolizing sacred traditional values in the field of education for the people of Vinh Long province. Stone steles recorded names of all contributors related to the construction and restoration of the temple with sincere gratitude. Moreover, many of the decorative motifs contain many indigenous cultural and artistic values of Vietnam, reflecting traditional Vietnamese beliefs and ethnographic features.Research limitations/implicationsBy comparatively analyzing the temple with others, it reveals the unique spatial features, layouts, changes and evolutions of the temple. Unlike the oldest and the largest Temple of Literature in Hanoi, the temples in the South are much smaller in terms of complex sizes and the number of buildings. They are mostly composed of a singular structure, the Attained Talent House, with some basic gates and water features interwoven within the landscape of the site. Based on the elementary layout, some subsidiary buildings were added according to the needs and site conditions, and in accordance with the bilateral axis.Social implicationsThe awareness and preservation of the architectural features of the local temple are needed to protect heritage monuments and to enhance cultural resources as part of securing Vietnamese ideology for a longer period of time. While the interest in historic preservation and conservation activities of heritage buildings in Vietnam has slowly grown in attention over the last decade, it is evident that many opportunities remain. It is hoped that this research is a small step toward further research, education and advocacy in the preservation of historic buildings in Vietnam.Originality/valueThe introduction of Chinese Confucian thought to Vietnam was one of the most substantial influences in Vietnamese intellectual history. Despite being an important part of the nation's architectural, cultural and intellectual heritage sites, the study and documentation of the Temples of Literature have been relatively neglected or marginalized. Accordingly, this study is significant to reveal not only the values and unique heritage characteristics of the temple, but also to prioritize resources for continued study and preservation.

Secure delegated quantum computation based on Z-rotation encryption

Quantum computing on encrypted data allows a client who has limited quantum capacity to delegate his or her private computation to an untrusted quantum server, while the input and output are encrypted by the quantum one-time pad and only the client can correctly decrypt them. Generally, the client is required to have ability to prepare some single qubits and perform some basic gates. In this work, we consider a further restricted situation where the client can only prepare one single qubit and perform one basic gate. Specifically, we show that as long as the client can prepare a fixed qubit and perform a fixed phase gate P, then he or she can still achieve the secure delegated quantum computation. Besides, our protocol can provide a more rigorous security for any quantum computation. For example, even if some encryption keys about the computation are leaked, it can still guarantee the privacy of the input and output. Finally, our protocol experimentally has a great significance in reducing the device complexity of the client's side.

Low power architecture of logic gates using adiabatic techniques

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

A quantum convolutional neural network on NISQ devices

Quantum machine learning is one of the most promising applications of quantum computing in the noisy intermediate-scale quantum (NISQ) era. We propose a quantum convolutional neural network(QCNN) inspired by convolutional neural networks (CNN), which greatly reduces the computing complexity compared with its classical counterparts, with O((log2M)6) basic gates and O(m2+e) variational parameters, where M is the input data size, m is the filter mask size, and e is the number of parameters in a Hamiltonian. Our model is robust to certain noise for image recognition tasks and the parameters are independent on the input sizes, making it friendly to near-term quantum devices. We demonstrate QCNN with two explicit examples. First, QCNN is applied to image processing, and numerical simulation of three types of spatial filtering, image smoothing, sharpening, and edge detection is performed. Secondly, we demonstrate QCNN in recognizing image, namely, the recognition of handwritten numbers. Compared with previous work, this machine learning model can provide implementable quantum circuits that accurately corresponds to a specific classical convolutional kernel. It provides an efficient avenue to transform CNN to QCNN directly and opens up the prospect of exploiting quantum power to process information in the era of big data.

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

Toward Quaternary QCA: Novel Majority and XOR Fuzzy Gates

As an emerging nanotechnology, quantum-dot cellular automata (QCA) has been considered an alternative to CMOS technology that suffers from problems such as leakage current. Moreover, QCA is suitable for multi-valued logic due to the simplicity of implementing fuzzy logic in a way much easier than CMOS technology. This paper uses a quaternary cell with two isolated layers because of requiring three particles to design this quaternary cell. Moreover, due to the instability of the basic gates, the three particles cannot be placed in one layer. The first layer of the proposed two-layer cell includes a ternary cell and the second one includes a binary cell. It is assumed that the overall polarization of the quaternary QCA (QQCA) cell is determined as the combined polarization of the two layers. The proposed QQCA cell can also be implemented in one layer. Simulations of the QQCA cell are performed based on analytical calculations. Moreover, a majority fuzzy gate, an XOR fuzzy gate, and a crossbar structure are simulated.

Memristor ratioed logic crossbar‐based delay and jump‐key flip‐flops design

AbstractMemristor has been widely explored in digital logic circuits where most of the works are focused on basic gate circuits, such as OR and AND logic gates or full adders while few involve flip‐flops. In fact, flip‐flops are also basic logic units with memory function for various digital systems. In this paper, we present circuit designs for Delay (D) and Jump‐Key (JK) flip‐flops based on memristor ratioed logic (MRL). The proposed circuit for D flip‐flop only needs five memristors and one NMOS transistor, and circuit for JK flip‐flop needs seven memristors and two NMOS transistors. Furthermore, the proposed circuits have been mapped into a hybrid memristor‐CMOS crossbar array. Compared with previous approaches, the quantity of MOSFET for each proposed circuit has been greatly reduced. Thus, the proposed designs have achieved simpler structure, smaller area, and lower power consumption benefiting from the memristor's nanoscale size and low power consumption. The circuit verification based on PSpice simulation is also provided.

Innovation Quinary and n‐Value toward Fuzzy Logic QCA Cell Design

AbstractQuantum Cellular automata (QCA) is a technology developed to replace complementary metal‐oxide‐semiconductor (CMOS) technology that faces increasing challenges due to the miniaturization of CMOS dimensions. The use of multi‐valued QCA is of interest because of its proximity to fuzzy logic, and lower power consumption. A two‐layer quinary system is proposed and the basic logic gates are examined and simulated to confirm the correct performance of the proposed cell. The proposed cell employs two layers because the presence of more than two particles per layer destabilizes the design of logic gates. The proposed Quinary QCA(QuQCA) cell can be implemented in one layer using input and output derives. Simple relationships are proposed to calculate the polarization values and the number and type of layers, so complex quantum computations can be avoided. The quantum power consumption and the proposed cell power consumption of the quinary system are calculated and compared. Finally, we present n‐valued cells without using quantum computation, and these cells are examined in terms of the number of particles, polarization value, and cell structure. The n‐level cell can be investigated more easily than other technologies due to its proximity to fuzzy logic and the design of the input, output, and fuzzy membership function.

Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization

Quantum Dot Cellular Automata or QCA is a promising transistor less nano-technology that is growing in popularity and it has the capability to replace the ubiquitous CMOS technology in the VLSI domain. The paper discussed the simple design of single bit comparator circuit using QCA. A single-bit comparator circuit compares its two inputs and indicates which one is larger or are they both equal. This paper has focused on creating an area efficient QCA comparator circuit and a comparative study of area consumption with the previously made designs. The designed comparator circuit is the most area-efficient design as it is made up of minimum possible number of cells. A Comparator is used in equality testers and many other digital communications The circuit proposed in this paper is a three layered circuit which can alternatively be used to realize the basic logic gates. The circuit can also be used as an alternative to the majority and universal gates in QCA.

Memoryless Logic Circuit Design Based on the Quantum Phase Slip Junctions for Superconducting Digital Applications

In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.

Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NOR Logic Gate using Open-Source Software eSim

Abstract: There are various basic gates like NAND, NOR gates which are extensively used in the designing of the more complex circuits with use higher number of transistors such as MUXs, ADCs and any other circuits. In this paper, we have carried out the modelling of NOR gate at 130 nm technology, yet maintaining comparable performance than conventional CMOS NOR gate logic structure. The modelling includes schematics design and PCB layout design run of the above gates. Also, the simulation results of the gates are obtained at the same node with start time, step time, stop time, rise time, fall time and delay and power dissipation. In this all process have been carried out of a CMOS based NOR Logic Gate using Open-Source Software eSim. Keywords: Simulation, PCB, NOR, CMOS, eSim

A Sustainable Method to Study Digital Logic Circuits Hands-on Activity Method Using Arduino

The purpose of this study is to propose a new, sustainable method for creating and studying digital logic circuits hands-on activity, using the Arduino open-source platform. For the purouse, in this study, based on the ADDIE model and the model of Lee (2020), a method of implementing a basic gate circuit with Arduino was presented. As a result of this study, it was confirmed that it is possible to implement sustainable digital logic circuit practice using Arduino. In addition, as a result of this study, circuit configuration method, wiring diagram, programming source code, application results, and other design details for the circuit using components such as the Arduino, buttons, and LEDs were presented. The method proposed in this study can be used in digital logic circuit hands-on classes for non-major university students, primary school students, and secondary school students, and can also be used in maker education, coding education, and software education. As this method needs only open-source hardware and software, such as Arduino and the C language, that are freely available, it can be used to practice making digital logic circuits in a sustainable way in the future.

Optical-switched proton logic gate: Indocyanine green decorated HSB-W5 MOFs nanosheets

Proton conduction controlled by light is important for advanced applications in sensors and information processing devices. We herein report a metal-organic framework (MOF) thin film by introducing indocyanine green dye into HSB-W5 (HSB = hydrogenated Schiff base) matrix (ICG@HSB-W5) to construct a series of basic logic gates (NOT, NAND, and NOR) on account of its good photothermal conversion ability and photo-controlled proton conductivity. The proton conductivity of ICG@HSB-W5 thin film is 25 times higher than that of the pristine HSB-W5 thin film and responses efficiently to lasers. In addition, the change of proton conductivity is very large with an ON/OFF ratio above 1000 and enough to be distinguished to build logic gates. In this logic gate system, 808- and 405-nm lasers are used as inputs and the proton conductivity is used as output signal with different thresholds. The electrical output signal is convenient and available to be received and detected. It offers a new route for the design of molecular logic gates based on MOF and facilitates the construction of proton-based logic gate or more complicated logic devices.

Basic Logic Operations Achieved in a Single 2D WSe2Transistor by Surface-Charge-Transfer Doping

A basic logic gate based on conventional silicon transistors needs the combination of at least two transistors in series or parallel. Two-dimensional (2D) materials with atomic thickness and flexib...

New polarization and power calculations with error elimination in ternary QCA

Quantum cellular automata (QCA) is a promising technology for replacing MOS transistors in digital and computing systems. Recently, many efforts have been made to design complex structures using Binary QCA (bQCA) cells, researchers’ attention has been drawn to multilevel structures using QCA technology, and Ternary QCA (TQCA) cells have been introduced. Many researchers have studied the structure of the TQCA cell, and several models have been proposed to design the AND and OR gates. This paper investigated the polarization in TQCA using two electron particles and eight potential wells. The distance between wells and the cell wall was also changed, and the error in the AND and OR gates was eliminated by using TQCA in one phase clock. In the following calculations, the power dissipation of TQCA cells in different polarizations and the upgrade of TQCA Sim software to implement basic gates using the performed calculations have been investigated.

Investigation of Power Consumption Effect of Various Memristor Emulators on a Logic Gate

Memristor, also known as memory resistor, is considered as the fourth passive electronic element expressing the relationship between magnetic flux and electric charge. One of the most important features of the memristor is that it has low power consumption. Minimizing power consumption is an important issue in the electronic circuits. However, the fact that the memristor element was not yet fully manufactured has led researchers to design memristor-like emulator circuits. These circuits, which approximate the memristor properties, are realized by combining the other existing electronic elements. In this paper, a basic NAND logic gate is considered and the change in power consumption when using a memristor instead of the standard resistor in the gate circuit is examined. For this purpose, the NAND logic circuit was constituted for four different memristor emulators, and the power consumption values of these circuits were obtained by simulation and experiments. These values are compared with the power consumption values of NAND circuits obtained by using standard resistors equivalent to the memristor resistance. The results clearly show that the memristor gate circuits reduce power consumption compared to standard resistive gate circuits.

IoT-Based Lab System for Teaching Methods in Times of Crisis

The revolution of communication technology has enabled people to communicate easily with others and perform many tasks from a distance. The Internet plays an important role in communication and helps to perform tasks and make people's lives easier. It led to the introduction of the Internet of Things (IoT) technology, where physical objects are connected to the Internet to perform a specific task. So that IoT can be a valuable tool in times of crisis, most modern industries can produce their products automatically and remote monitor and control the system. The same technique can be applied to overcome face-to-face teaching in science and engineering education during times of crisis. This research proposes the design and development of an IoT-based hands-on laboratory system that can be operated remotely. The methodology has been implemented and worked based on the concept of virtual reality. The research has been carried out for two simple electrical laboratory experiments: the basic logic gate and Ohm’s Law experiment. The experimental results show that the system can be implemented since the results obtained are satisfy their theoretical results. Furthermore, an improvement can be made so that the system can be integrated with the Internet and the system can function efficiently.