Abstract
Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.
Highlights
Two major problems are facing the embedded systems and nano-scale circuits currently, which are (1) the CMOS (Complementary Metal Oxide Semiconductor) transistor, and (2) the binary circuits
Solutions can be done by using Carbon nano-tube field effect transistors (CNTFET) (Carbon Nano-Tube Field Effect Transistor) instead of CMOS transistor and using MVL (Multiple-Valued Logic) circuits instead of binary circuits
This paper proposes efficient circuit implementation of ternary half adder (THA) and ternary multiplier (TMUL) with 35 and 26 CNTFETs using unary operators, transmission gates, and dual-voltages (Vdd, Vdd/2) to get the lowest power-delay product (PDP) for saving battery consumption of the embedded systems and Internet of Thing (IoT) devices
Summary
Two major problems are facing the embedded systems and nano-scale circuits currently, which are (1) the CMOS (Complementary Metal Oxide Semiconductor) transistor, and (2) the binary circuits. This paper utilizes the ternary unary operators (see Section II), CNTFET transistor, transmission gates and applies dual-voltages (Vdd, Vdd/2) in the designs to decrease the PDP of the proposed THA and TMUL. This technique is used to save battery consumption of the nano-scale embedded systems and Internet of Thing (IoT) devices. This paper proposes efficient circuit implementation of THA and TMUL with 35 and 26 CNTFETs using unary operators, transmission gates, and dual-voltages (Vdd, Vdd/2) to get the lowest PDP for saving battery consumption of the embedded systems and IoT devices. We reduce the transistors count, decrease the energy consumption, improve the robustness to process variations, and noise tolerance
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