Modeling the Characteristics of SOI CMOS Nanotransistors with an Asymmetric Surrounding Gate

Abstract

An approach to an end-to-end simulation of the electrophysical characteristics of lowly doped sub-25-nm SOI (silicon-on-insulator) CMOS transistors with an asymmetric surrounding gate composed of two sequentially connected materials with different work functions is considered. The approach consists of the consecutive calculation of the 3D potential distribution in the working region, calculation of the current–voltage characteristics, and calculation of the static and dynamic characteristics for a basic logic gate (an inverter). In the context of the discussed approach, the effect of the ratio between the lengths of the gate regions with different work functions on all the key characteristics of the devices (transistors and logic gates based on them) are analyzed. It is demonstrated that the logic gates can operate efficiently at a supply voltage of 0.8 V, which is a prerequisite for the creation of low-voltage circuit engineering.