UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

Abstract

In this work, design and measurement results of UHF RF frontend circuits to be used in low-IF and subsampling receiver architectures are presented. We report on three low noise amplifiers (LNA) (i) single-ended (ii) differential (iii) high-gain differential and a double-balanced mixer all implemented in 0.35-μm SOI (Silicon on Insulator) CMOS technology of Honeywell. These circuits are considered as candidate low-power building blocks to be used in the two fully-integrated receiver chips targeted for deep space communications. Characteristics of square spiral inductors with high quality (Q) factors (as high as 10.8) in SOI CMOS are reported. Single-ended and fully-differential LNA's provide gains of 17.5 dB and 18.74 dB at 435 MHz, respectively. Noise figure of the single-ended LNA is 2.91 dB while the differential LNA's noise figure is 3.25 dB. These results were obtained for the power dissipations of 12.5 mW and 16.5 mW from a 2.5-V supply for the single-ended and differential LNA's, respectively. High-gain low-power differential LNA provides a small-signal gain of 45.6 dB with a noise figure of 2.4 dB at 435 MHz. Total power dissipation of the high gain LNA is 28 mW from a 3.3-V supply. The double-balanced mixer provides a conversion gain of 5.5 dB with a noise figure of 13 dB at 2 MHz IF. The power dissipation of the mixer is 11.5 mW from a 2.5-V supply. The measured responses and the power dissipations of the building blocks meet the requirements of the communications system. The die areas occupied by the single-ended LNA, differential LNA, high-gain LNA and the mixer are 0.6mm × 1.4mm, 1mm × 1.4mm, 1.4mm × 1.2mm and 0.6mm × 0.9mm, respectively.