A low-power low-noise amplifier in 0.35-μm SOI CMOS technology

Abstract

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-/spl mu/m silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of -12.5 dBm, input third-order intercept point of -5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm /spl times/ 0.58 mm. Due to high-resistivity silicon substrate and buried oxide isolation, SOI CMOS technology offers significant performance improvements for mixed-signal VLSI and RF/Microwave integrated circuits.