Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors

Abstract

Summary form only given. Silicon-on-insulator (SOI) CMOS technology has proven to be compatible with bulk CMOS in many ways, ranging from circuit design and layout to wafer processing. In addition, partially-depleted (PD) SOI technology has been suggested as a method for achieving a high circuit performance at low supply voltage and low power (Jacobs et al, 1998). Unlike fully-depleted (FD) SOI transistors, PD SOI devices have the advantage of a threshold voltage V/sub T/ which is insensitive to variations in the silicon thickness uniformity. Based on device physics, the long-channel threshold voltage V/sub T/ is equal to the V/sub T/ of the bulk transistor as long as the channel doping concentrations are equal. Therefore, PD SOI CMOS design appears to be very similar to conventional bulk. Often, the design of a PD SOI CMOS technology is started from a present and well-known baseline bulk CMOS technology. During device fabrication, it is assumed, however, that the diffusivity of the channel dopants in the vertical direction in SOI is similar to bulk, which is fundamentally incorrect. In order to investigate the threshold voltage difference between PD SOI and bulk, SOI CMOS transistors have been fabricated on BESOI wafers with buried oxide and silicon layer thicknesses of 350 and 125 nm, respectively. In order to obtain a straight comparison with the bulk CMOS technology, each SOI wafer has a bulk counterpart for which the process conditions have been exactly the same.