Analog performance of PD-SOI MOSFETs at high temperatures using reverse body bias

Abstract

The analog performance, i.e. intrinsic gain and bandwidth, of SOI (Silicon-on-Insulator) MOSFETs in a wide temperature range up to 400°C has so far been strongly affected by device leakage currents. Thereby the moderate inversion region as a preferred point of operation has been unusable as leakage currents dominate drain currents at high temperatures. In this paper we present a reverse body biasing (RBB) approach to improve the transistor's analog performance up to 400°C. Thereby operation in the lower moderate inversion region of the SOI transistor device is feasible. The method allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD (partially depleted) SOI CMOS process. NHGATE and PHGATE devices with an H-shaped gate have been investigated. Results report a significant improvement of the gm/Id factor and the intrinsic gain Ai in the moderate inversion region by applying RBB.