Base-collector Junction Capacitance Research Articles

A complete small-signal HBT model including AC current crowding effect

An improved small-signal equivalent circuit of HBT concerning the AC current crowding effect is proposed in this paper. AC current crowding effect is modeled as a parallel RC circuit composed of C bi and R bi, with distributed base-collector junction capacitance also taken into account. The intrinsic portion is taken as a whole and extracted directly from the measured S-parameters in the whole frequency range of operation without any special test structures. An HBT device with a 2 × 20 μm2 emitter-area under three different biases were used to demonstrate the extraction and verify the accuracy of the equivalent circuit.

(Invited) Physics and Compact Modeling of Sige HBT Linearity

SiGe HBTs, like other semiconductor devices, are in general nonlinear circuit elements. The exponential IC-VBE nonlinearity common to all bipolar transistors represents the strongest possible nonlinearity for all devices in which currents are produced by drift and diffusion of electrons and holes. Nonlinearity is desired for frequency translation and oscillation, but undesired for signal reception, amplification and transmission. In this talk we will review the fundamentals of various physical nonlinearities in SiGe HBTs, their complex interactions, experimental biasing current and voltage dependence of 2nd and 3rd order intercept points, IP2 and IP3, as well as recent developments in compact modeling of linearity using Mextram, an industry standard transistor model we are developing, for both common-base and common-emitter configurations. From a circuit point of view, the consequence of nonlinear IC-VBE is to make effective transconductance gm,eff a function of small signal base-emitter junction voltage vbe , as opposed to a constant in a linear circuit. The nonlinear contributions in general increase with vbe, which in general decreases with increasing biasing current before high injection, making gm,eff closer to a constant. The linearity of a SiGe HBT amplifier can therefore generally be improved by increasing biasing current. At radio frequencies, however, at relatively higher current, the 3rd order current produced by the nonlinear base-collector junction capacitance becomes important, and can interact with the 3rd order currents produced by the nonlinear IC, leading to a peak of IP3. Likewise, at higher VCB, as found in the common-base stage of a cascode amplifier, avalanche multiplication current Iavl produces an important 3rd order current that interacts with 3rd order currents from IC (without avalanche) and CBC, which can lead to a peak of IP3 in VCB dependence. Such peaks of IP3 are important for transistor biasing and sizing in circuit design, but also pose more stringent requirements on compact modeling than DC I-V and linear s-parameters. While both CBC and Iavl are straightforward to characterize and model at low currents, difficulties in both characterization and modeling increase at higher currents of interest. Latest Mextram 505.00 provides several options for modeling VCB and IC dependence of CCB, which give similar y-parameters but different IP3, particularly for common-emitter configuration, as illustrated in Figure 1. New CCB model options for junction voltage and capacitance smoothing, swvjunc=1, swvchc=0, lead to much better modeling of peak OIP3 than swvjunc=2, swvchc=1, which reduces to 504.12. Recommendations of best options and parameters for accurate modeling of IP3 will be made. While CCB model also affects IC nonlinearity through Early effect, we will show that its impact on IP3 is primarily through capacitive current. We will also show that the IC dependence of CCB is import to include for IP3. Common-base transistors often operate at higher VCB and hence with significant amount of Iavl. Mextram 505.00 has a new Iavl model that allows better current dependence and temperature dependence. Figure 2 shows this new avalanche model (swavl=1) has improved current dependence modeling of OIP3 over 504.12 (swavl=2 reduces model to 504.12) for a common-base SiGe HBT. Figure 1

Direct Extraction Method of HBT Equivalent-Circuit Elements Relying Exclusively on $S$-Parameters Measured at Normal Bias Conditions

A new direct parameter-extraction scheme applied to a heterojunction bipolar transistor (HBT) small-signal equivalent circuit with distributed base-collector junction capacitance is presented. The proposed method relies exclusively on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters measured at low and high frequencies in normal bias conditions, and without using approximations based on anticipated values. The extraction results obtained from low-frequency modeling allow the extraction of the parasitic inductances at high frequency. This is performed by formulating expressions based on ac-current-source consideration different from the previously published one, without affecting the physical signification of the HBT model. This method presents a simple way for the extraction of the model parameters directly. An experimental validation on an InP double HBT device was carried out, using the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters measured in a frequency range of 40 MHz-50 GHz over a wide range of bias points. The modeling results are presented, showing that the proposed method can yield a good fit between measured and calculated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters.

A physical-model of small-signal InP-based double heterojunction bipolar transistors and its parameter extraction technique

The influence on the base-collector junction capacitance Cbc of the energy band structure of the InP heterojunction bipolar transistors is researched. A physical model of small-signal InP double heterojunction bipolar transistor （DHBT） is developed, which takes into account the base-emitter and collector-emitter metalisations by using two additional capacitances Cmb and Cmc. The resistance of the model is divided into the intrinsic resistance, the extrinsic resistance and the parasitic resistance. Meanwhile, a physically meaningful small-signal parameter extraction procedure for the model is presented, in which all the equivalent circuit elements are extracted without reference to numerical optimization. An experimental validation is carried out, and excellent results are obtained over a wide range of bias points, which demonstrates good modeling accuracy.

A compact model for SiGe HBT on thin-film SOI

Heterojunction bipolar transistor (HBT) fabrication on thin-film silicon-on-insulator (SOI) has been recently demonstrated. Due to the space volume constraint (thin film) for the device fabrication, the HBT structure is different from bulk HBT. In fact, compared to a bulk device, the buried layer has been suppressed and a lateral collector contact configuration is introduced. This device features a vertical expansion followed by a lateral expansion of the base-collector space charge region. This nonconventional charge behavior induces a kink in the base-collector junction capacitance characteristics, and as a consequence a modified Early effect. Furthermore, the low current transit time is modified compared to a bulk HBT. In this paper, all these effects are analyzed and a compact model for SOI-HBT is proposed. The model is validated on real SOI-HBTs with different collector doping levels.

G-band (140-220-GHz) InP-based HBT amplifiers

We report tuned amplifiers designed for the 140-220-GHz frequency band. The amplifiers were designed in a transferred-substrate InP-based heterojunction bipolar transistor technology that enables efficient scaling of the parasitic collector-base junction capacitance. A single-stage amplifier exhibited 6.3-dB small-signal gain at 175 GHz. Three-stage amplifiers were subsequently fabricated with one design demonstrating 12.0-dB gain at 170 GHz and a second design exhibiting 8.5-dB gain at 195 GHz.

Low noise 5 GHz differential VCO using InGaP/GaAs HBT technology

The authors present the first InGaP/GaAs HBT differential VCOs with low phase noise performance. One is a cross coupled differential VCO, and the other is a Colpitts differential VCO. To achieve a fully integrated VCO, collector-base junction capacitance of HBT transistor is used for the frequency tuning varactor. The measured output frequency ranges of VCOs are 290 MHz and 190 MHz, and the phase noises at an offset frequency of 1 MHz are -118 dBc/Hz and -117 dBc/Hz respectively. The each VCO core dissipates 13.2 mW from a 3.5 V supply, and the output power is about -0.2 dBm. Concerned with cross coupled VCO, it shows the figure of merit of -179 dBc/Hz, which is the best result among the reported compound semiconductor FET and HBT VCOs.

Base resistance variation of AlGaAs/GaAs HBT by He + ion implantation

Reduction of base–collector junction capacitance has been intended by He + ion implantation to enhance the maximum oscillation frequency of AlGaAs/GaAs heterojunction bipolar transistors (HBTs). From the recovery of the base resistance by rapid thermal annealing (RTA) after ion implantation, it is found that optimum conditions are 140 keV and 5×10 12–1×10 13 cm −2 for He + ion implantation and 400°C and 20 s for rapid thermal annealing.

Extrapolated f/sub max/ of heterojunction bipolar transistors

It is shown that the extrapolated f/sub max/ of heterojunction bipolar transistors (HBT's) can be written in the form f/sub max/=/spl radic/f/sub T//8/spl pi/(RC)/sub eff/, where f/sub T/ is the common-emitter, unity-current-gain frequency, and where (RC)/sub eff/ is a general time constant that includes not only the effects of the base resistance and collector-base junction capacitance, but also the effects of the parasitic emitter and collector resistances, and the dynamic resistance 1/g/sub m/, where g/sub m/ is the transconductance. Simple expressions are derived for (RC)/sub eff/, and these are applied to two state-of-the-art devices recently reported in the literature. It is demonstrated that, in modern HBT's, (RC)/sub eff/ can differ significantly from the effective base-resistance-collector-capacitance product conventionally assumed to determine f/sub max/.

Unified HBT base push-out and base-collector capacitance model

The presence of electron space-charge in the collector region of a transistor has the effect of offsetting the collector doping thereby giving a reduced effective doping concentration. This effect can modify the base-collector junction capacitance and for high current densities will give rise to base push-out. This paper describes the implementation of a unified junction capacitance and push-out model for the microwave HBT biased in the forward active mode. The threshold functions for pushout and full collector depletion are given and their significance for device and circuit design is discussed. An approximate description of the effect of pushout on the HBT forward time constant is described which accounts for the substantially increased diffusion constant in the pushout region.

Theoretical and Experimental Study of High-Energy Implanted Collectors for Bipolar Transistors in Bipolar-Complementary Metal Oxide Semiconductor Transistor Technology

This work is a theoretical and experimental study of the properties of retrograde collector profiles for bipolar transistors produced using high-energy ion implantation. One-dimensional device simulations are carried out, and show that compared with a uniform profile, the retrograde profile allows transistor operation at higher current levels without incurring an unacceptable increase in the base-collector capacitance. Two-dimensional process and device simulations are also carried out to analyze the two-dimensional electrical behavior of the retrograde collector. At low collector-emitter bias, quasi saturation is observed due to the vertical drop in potential, which is associated with a lateral drop in the potential in the collector resistance, and must be minimized. At high collector-emitter bias, the injection regime, resulting from the Kirk effect, occurs. Experimental bipolar transistors are designed and fabricated based on these simulation results. The proposed self-aligned design minimizes both the extrinsic base-collector junction capacitance and the series collector resistance. A measured transit frequency (f T) of 7.8 GHz is obtained, which is ample for many analog and digital VLSI circuits which require operating frequencies up to a few gigahertz.

Avalanche breakdown effects on AlGaAs/GaAs HBT performance

The performance of heterojunction bipolar transistors operating in the avalanche breakdown regime has been evaluated. The analysis shows that AlGaAs/GaAs HBT under avalanche breakdown has higher collector-base junction capacitance, lower Early voltage, higher device noise, lower power efficiency, lower cut-off frequency, reduced device switching speed, and degraded maximum frequency of oscillation.

Collector–Base Junction Capacitance of Advanced Bipolar Transistors Operating at Avalanche Breakdown

Modeling of the collector–base junction capacitance of the advanced bipolar transistors operating at avalanche breakdown is developed. The comprehensive junction capacitance model accounts for high current and high field effects at the collector–base junction. The impact ionization generates tremendous amount of free carriers in the collector–base space-charge region which increases the collector–base junction capacitance at the avalanche breakdown regime. The present collector–base junction capacitance is useful for device and circuit design under avalanche breakdown prior to the actual fabrication of the circuit.

Large signal modeling of HBT's including self-heating and transit time effects

A physically based, large signal heterojunction bipolar transistor (HBT) model is presented to account for the time dependence of the base, collector, and emitter charging currents, as well as self heating effects. The model tracks device performance over eight decades of current. The model can be used as the basis of SPICE modeling approximations, and to this end, examples are presented. A thesis for the divergence of high frequency large signal SPICE simulations from measured data is formulated, including a requisite empirical equation for the base-collector junction capacitance. >

Modeling the current-dependent [formula omitted] for AlGaAs/GaAs heterojunction bipolar transistor design

The modeling of current-dependent cut-off frequency ƒ T for AlGaAs/GaAs heterojunction bipolar transistors has been investigated. The analytical equations developed account for high-current base widening, current-dependent collector-base junction capacitance, and proton and nonproton implanted collectors. The ballistic transport and velocity overshoot effects are accounted for in the modeling equations. Experimental results reported in the literature are compared in support of the model utility and accuracy. Optimization of heterojunction bipolar transistor design is discussed based on current-dependent ƒ T analysis.

Transit frequency of fast Si self-aligned bipolar transistors

The small-signal current gain beta of fast Si self-aligned transistors is measured up to the transit frequency f/sub T/ using a 26.5-GHz microwave network analyzer system and special HF measuring probes. The influence of parasitic transistor elements such as the base-collector junction capacitance, the internal base resistance, and the peripheral transistor was confirmed in a real transistor at high frequencies by measurements on transistors with different emitter areas. The two-dimensional effects, which deviate from the expected one-pole frequency behavior of beta , can be described by the extended transistor model, namely the intrinsic model and the peripheral model. >

Comments on "A compact physical large-signal model for high-speed bipolar transistors at high current densities-part I: one-dimensional model" (by H.-M. Rein et al., with reply)

The junction space-charge-region capacitances are of primary importance for high-speed VLSI bipolar circuit modeling. It is shown in the above paper that the emitter-base junction capacitance model is compact and is in excellent agreement when compared with other relatively complicated models and methods. However, the base-collector junction capacitance model is questionable in the sense that the base-collector junction capacitance becomes more important, rather than being negligible, as suggested by Stubing and Rein, in the high current region. In reply, Rein et al. show that their model is admissible, and give some remarks on Liou's additional comments. Since the transistor model was developed for high-speed ICs, the numerical examples presented are typical for such circuits. This means, e.g., that the specific resistances and the effective thicknesses of the epitaxial collector are more than about ten times lower than in the example given by Liou.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Base-collector junction capacitance of bipolar transistors operating at high current densities

An analytical physics-based comprehensive base-collector junction capacitance model is presented. The model, which includes high-current effects, describes the base-collector space-charge-region capacitance for all operating regions, including the saturation region in which the space-charge region becomes forward biased. The present model is compared with the depletion capacitance model and significant discrepancies are predicted. An emitter-coupled logic gate circuit is used to demonstrate the practical usefulness of the model.

High Speed Bipolar ICs Using Super Self-Aligned Process Technology

We have developed a new bipolar process technology, called SST. The emitter region, base p region, base p+ region, base p+ polysilicon electrode and emitter contact window of NPN transistor are formed by one mask photolithography process. The transistor active regions are all self-aligned. Therefore, small-size transistors can be realized and high performance is achieved by the decreased collector-base junction capacitance. A new bipolar integrated circuit using SST gave a 63 ps/gate propagation delay time and 0.043 pJ/gate speed-power product.

IF Amplifier using C/SUB c/ compensated transistors

An integrated bridge network of four transistors is used as a self-neutralized active element in tuned RLC amplifier designs. The bridge network compensates for the transistor collector-base junction capacitance (C/SUB c/), yielding a 95-percent reduction in the common-emitter reverse transmission admittance. IF amplifier stages that achieve the maximum unilateral power gain of a common-emitter transistor while maintaining excellent alignability are realized using the C/SUB c/ compensated transistor structure. Variations of the relative bias current levels of the transistors in the bridge network provides gain control by way of signal cancellation. This technique produces minimal frequency response variations of the amplifier stage being controlled. A noise analysis shows output signal to noise ratio at maximum attenuation can be a performance limitation.