Back-gate Bias Research Articles

Inducing and Manipulating Heteroelectronic States in a Single MoS_{2} Thin Flake.

By dual gating a few-layer MoS_{2} flake, we induce spatially separated electronic states showing superconductivity and Shubnikov-de Haas (SdH) oscillations. While the highly confined superconductivity forms at the K/K^{'} valleys of the topmost layer, the SdH oscillations are contributed by the electrons residing in the Q/Q^{'} valleys of the rest of the bottom layers, which is confirmed by the extracted Landau level degeneracy of 3, electron effective mass of 0.6m_{e}, and carrier density of 5×10^{12} cm^{-2}. Mimicking conventional heterostructures, the interaction between the heteroelectronic states can be electrically manipulated, which enables "bipolarlike" superconducting transistor operation. The off-on-off switching pattern can be continuously accessed at low temperatures by a field effect depletion of carriers with a negative back gate bias and the proximity effect between the top superconducting layer and the bottom metallic layers that quenches the superconductivity at a positive back gate bias.

Leakage Current and Low-Frequency Noise Analysis and Reduction in a Suspended SOI Lateral p-i-n Diode

In this paper, we present a detailed analysis of leakage current in a silicon-on-insulator (SOI) lateral P+P−N+ (p-i-n) diode suspended on a microheating platform, combining device experimental characterization and numerical simulation. The diode leakage currents have been extensively studied using the back-gate bias as a means to alter the space-charge (SC) condition at the P− region (I-region)/buried oxide interface from accumulation to full depletion, and finally to inversion. Both dark leakage current analysis and low-frequency noise characterization performed on the suspended SOI lateral p-i-n diode indicate device degradation induced by microelectromechanical systems postprocessing (i.e., deep reactive-ion etching or aluminum deposition). A low-temperature (~250 °C) in situ (i.e., using embedded microheater) annealing of SOI lateral p-i-n diode after postprocessing allows reduction of the diode leakage current and optimization of the device performance by neutralizing the interface traps and improving carriers’ lifetime and surface recombination velocity. Numerical simulations have been performed with Atlas/SILVACO for deeper analysis of the leakage current behavior in the lateral p-i-n diode and identification of the generation mechanism dominating the diode leakage behavior. Simulation reveals that the dominant generation rate in the diode depends on the SC conditions, the interface trap density, and the carriers’ lifetime in the I-region. The experimental and simulated behaviors of “as processed” and annealed diode leakage current are shown to be in good qualitative agreement.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Dopant induced single electron tunneling within the sub-bands of single silicon NW tri-gate junctionless n-MOSFET

We report 1D electron transport of silicon junctionless tri-gate n-type transistor at 4.2 K. The step like curve observed in the current voltage characteristic suggests 1D transport. Besides the current steps for 1D transport, we found multiple spikes within individual steps, which we relate to inter-band single electron tunneling, mediated by the charged dopants available in the channel region. Clear Coulomb diamonds were observed in the stability diagram of the device. It is shown that a uniformly doped silicon nanowire can provide us the window for the single electron tunnelling. Back-gate versus front-gate color plot, where current is in a color scale, shows a crossover of the increased conduction region. This is a clear indication of the dopant–dopant interaction. It has been shown that back-gate biasing can be used to tune the coupling strength between the dopants.

Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design.

The total ionizing dose response of a DSOI 4Kb SRAM

A 4K-bit SRAM with 0.2um Double Fully-Depleted Silicon-On-Insulator (DSOI) CMOS process is designed to examine circuit total ionizing dose (TID) and the back gate bias effect. Preview researches show that MOSFET electrical parameter shift due to TID damage can be compensated by back gate bias of the FDSOI technology. We can control the NMOS/PMOS back gate separately and discretionarily with DSOI structure which could improve circuit radiation tolerance. TID experiment results show that the total ionizing dose capability of the 4Kb SRAM test chip is above 1M rad (Si).

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

In brief

PAGE 847 Researchers in Taiwan have proposed a Class-C differential voltage-controlled oscillator (VCO) with dynamic back-gate bias. The VCO is designed and implemented in 0.18µm BiCMOS process, and they have demonstrated that the VCO dramatically minimizes start-up time and power consumption. PAGE 826 A high-gain antenna has been developed by researchers in Korea. The design achieves high efficiency and low sidelobe level, whilst easily managing dual-orthogonal polarisation through distributing the phase difference to only two ports. The work can be applied to smart wireless backhaul systems and massive MIMO antennas. VCOs are vital components in wired and wireless communication systems PAGE 856 By incorporating an empirical noise model in the image generation process, researchers in Denmark have developed a method for generating synthetic Kinect v1 depth images with a high degree of realism. This technique can be used in, for example, the training of algorithms, analysis of uncertainties, evaluation of algorithms, analysis of visual features, and offline programming or prototyping. The cross-dipole antenna shows strong performance in terms of impedance, bandwidth, gain and isolation PAGE 885 Researchers from China have calculated the coverage probability of wireless data transmission between multiple unmanned aerial vehicles (UAVs). Using frequency bandwidth dependent models for air and ground communication channels, the method defines guidelines for optimising the design of aerial networks between multiple UAVs. Results show the optimum distribution and altitude of UAV networks to maximise communication capacity in disaster response. The Kinect can be used in a surprising number of applications, from training of algorithms to online programming PAGE 881 Research from China proposes a new approach to expand GaAs Schottky diode modelling. The complexities associated with existing 3D Schottky diode models are reduced by setting the same permittivity values for approximate materials. Experimental measurements demonstrate the accuracy of the proposed model. The method provides a simple but accurate approach for predicting device performance of a Schottky diode. A generalised approach for using unmanned vehicles for wireless data transmission A new efficient modelling approach for predicting Schottky diode device performance

Low‐phase noise Class‐C VCO with dynamic body bias

A 2.5 GHz Class-C voltage-controlled oscillator (VCO) with dynamic back-gate-biased MOSFET is proposed. A dynamic gate biasing circuit is used to reduce power consumption by switching N-type MOS from initial Class-AB to Class-C operation in steady state. Moreover, the VCO uses dynamic back-gate bias to reduce threshold voltage of switching MOSFET during the start-up oscillation. The Class-C differential VCO is implemented in TSMC 0.18 μm bipolar-complementary-metal-oxide-semiconductor (BiCMOS) process. The measured phase noise is -124.8 dBc/Hz at 1 MHz offset frequency from 2.48 GHz carrier while consuming 2.64 mW power from a 0.8 V supply. Tuning range of VCO is 0.72 GHz, from 2.48 to 3.3 GHz, whereas the control voltage was tuned from 0 to 2 V. The VCO occupies a chip area of 446 × 840 μm 2 and provides a figure of merit of -197.55 dBc/Hz.

Monolayer Solid-State Electrolyte for Electric Double Layer Gating of Graphene Field-Effect Transistors.

The electrostatic gating of graphene field-effect transistors is demonstrated using a monolayer electrolyte. The electrolyte, cobalt crown ether phthalocyanine (CoCrPc) and LiClO4, is deposited as a monolayer on the graphene channel, essentially creating an additional two-dimensional layer on top of graphene. The crown ethers on the CoCrPc solvate lithium ions and the ion location is modulated by a backgate without requiring liquid solvent. Ions dope the channel by inducing image charges; the doping level (i.e., induced charge density) can be modulated by the backgate bias with the extent of the surface potential change being controlled by the magnitude and polarity of the backgate bias. With a crown ether to Li+ ratio of 5:1, programming tests for which the backgate is held at -VBG shift the Dirac point by ∼15 V, corresponding to a sheet carrier density on the order of 1012 cm-2. This charge carrier density agrees with the packing density of monolayer CoCrPc on graphene that would be expected with one Li+ for every five crown ethers (at the maximum possible Li+ concentration, 1013 cm-2 is predicted). The crown ethers provide two stable states for the Li+: one near the graphene channel (low-resistance state) and one ∼5 Å away from the channel (high-resistance state). Initial state retention measurements indicate that the two states can be maintained for at least 30 min (maximum time monitored), which is 106 times longer than polymer-based electrolytes at room temperature, with at least a 250 Ω μm difference between the channel resistance in the high- and low-resistance states.

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Two-dimensional (2D) analytical models for the subthreshold current and␣subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable␣boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

Charge Transport in MoS2/WSe2 van der Waals Heterostructure with Tunable Inversion Layer.

Despite numerous studies on two-dimensional van der Waals heterostructures, a full understanding of the charge transport and photoinduced current mechanisms in these structures, in particular, associated with charge depletion/inversion layers at the interface remains elusive. Here, we investigate transport properties of a prototype multilayer MoS2/WSe2 heterojunction via a tunable charge inversion/depletion layer. A charge inversion layer was constructed at the surface of WSe2 due to its relatively low doping concentration compared to that of MoS2, which can be tuned by the back-gate bias. The depletion region was limited within a few nanometers in the MoS2 side, while charges are fully depleted on the whole WSe2 side, which are determined by Raman spectroscopy and transport measurements. Charge transport through the heterojunction was influenced by the presence of the inversion layer and involves two regimes of tunneling and recombination. Furthermore, photocurrent measurements clearly revealed recombination and space-charge-limited behaviors, similar to those of the heterostructures built from organic semiconductors. This contributes to research of various other types of heterostructures and can be further applied for electronic and optoelectronic devices.

Quantum Efficiency Improvement of SOI p-i-n Lateral Diodes Operating as UV Detectors at High Temperatures

Thin-film lateral SOI p-i-n diodes can be used as photodetectors especially in the wavelength range of blue and ultra-violet (UV) radiation. Unlike vertical devices, lateral diodes can have depletion regions very close to the device surface, where the absorption of low-wavelengths radiation takes place. Due to this proximity to the surface, an MOS back-gate can control the charge density inside this region, allowing quantum efficiency improvement. This paper reports experimental results of SOI p-i-n photodetectors with different intrinsic lengths in the 300-500-K range, simultaneously considering back-gate bias and temperature influences. Indeed, the back-gate bias becomes very effective in terms of quantum efficiency control with up to 52.4% for $\text {L$_{\mathrm {I}}$}=1\mu \text{m}$ at $T=500$ K in inversion mode, while in accumulation, the resulting efficiency was 48.2% at $T=500$ K for the device with $\text {L$_{\mathrm {I}}$}= 10\,\,\mu \text{m}$ at UV. These variations are related to the behavior of dark current and the recombination rate of the devices.

Enhanced sensitivity mediated ambipolar conduction with p-type TiO2 anatase transducer for biomarker capturing

Field-effect transistor biosensors have attracted tremendous interests in the field of diagnosis due to their appealing characteristics such as high sensitivity, label-free detection and low-cost. In addition, their compatibility with the existing complementary metal oxide semiconductor technology has made them feasible for miniaturization, standardization, mass production and integration of readout circuitry compared to other bio-sensing technologies. Coupled with additional voltage biasing, FET prevails its versatility in terms of electrical modulation i.e. ambipolar conduction (holes or electrons that depend on additional voltage biasing). In this work, the field-effect transistor based biosensor was fabricated by using the silicon-on-insulator wafer. To utilize the sensing area, the titanium dioxide thin film was deposited on the channel area, in-between the source and drain. The atomic force microscopy, scanning electron microscopy, and X-ray diffraction were used to characterize the physical structure of the device and TiO2 anatase thin film. The surface functionalized specific functional groups were determined by using the Fourier transform infrared spectroscopy and X-ray photoelectron spectroscopy. Finally, the electrical characteristic with back-gate biasing was conducted for the detection of cardiac troponin I. It was observed that the significant amplification signal with back-gate biasing of −3V with the detection limit of 0.238ng/ml and increased sensitivity to 2.438μA(g/ml)−1 can be achieved with ambipolar conduction. This brings to a conclusion that the back-gated field-effect transistor is a promising approach for enhancing the sensitivity of the FET-based biosensors.

N-type polymeric organic flash memory device: Effect of reduced graphene oxide floating gate

In this paper, n type nonvolatile memory devices were fabricated by implanting a bilayer (rGO sheets/Au NP) floating gates, using n-type polymer semiconductor, poly {[N, N′ bis (2octyldodecyl) - naphthalene-1, 4, 5, 8 - bis (dicarboximide)-2,6-diyl] – alt - 5,5′ - (2, 2′ bithiophene)} [P(NDI2OD-T2)n]. In the developed organic field effect transistor memory devices, electrons are trapped/detrapped in rGO sheet/Au NP's nano-floating gates by controlling the charge carrier density in the active layer through back gate bias control. The devices showed interesting non-volatile memory properties with a large memory window of ∼34 V, a programming-reading-erasing cycling endurance of 103 times and most importantly, an improved retention time characteristics estimated by extrapolation (longer than the technological requirement of commercial memory devices (>10 years)). This approach provides a great potential for fabricating high-performances organic nano-floating gate memory devices and opens up a new way for the development of next-generation non-volatile memory devices.

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Total Ionizing Dose (TID) Effects in Ultra-Thin Body Ge-on-Insulator (GOI) Junctionless CMOSFETs With Recessed Source/Drain and Channel

Total ionizing dose (TID) effects in ultra-thin body Ge on Insulator (GOI) junctionless CMOSFETs with recessed source/drain and channel have been studied. 10-keV X-ray irradiation leads to net hole trapping at the top and bottom Ge/dielectric interfaces of both GOI NFETs and PFETs. The Ge channel thickness and post-oxidation processing can strongly affect the radiation response. Application of negative back-gate bias can moderate the radiation-induced threshold-voltage shifts.

Characterization and Modeling of NBTI in Nanoscale UltraThin Body UltraThin Box FD-SOI MOSFETs

The negative bias temperature instability (NBTI) is investigated in ultrathin body ultrathin box (UTBB) fully depleted silicon-on-insulator (FD-SOI) p-MOSFETs with zero back gate bias and small drain bias voltage. The threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by the trapping of holes in preexisting traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. Considering the hole-trapping/detrapping mechanisms, NBTI modeling has been proposed capturing the temperature and gate voltage dependence.

A Dynamically Reconfigurable Ambipolar Black Phosphorus Memory Device.

Nonvolatile charge-trap memory plays an important role in many modern electronics technologies, from portable electronic systems to large-scale data centers. Conventional charge-trap memory devices typically work with fixed channel carrier polarity and device characteristics. However, many emerging applications in reconfigurable electronics and neuromorphic computing require dynamically tunable properties in their electronic device components that can lead to enhanced circuit versatility and system functionalities. Here, we demonstrate an ambipolar black phosphorus (BP) charge-trap memory device with dynamically reconfigurable and polarity-reversible memory behavior. This BP memory device shows versatile memory properties subject to electrostatic bias. Not only the programmed/erased state current ratio can be continuously tuned by the back-gate bias, but also the polarity of the carriers in the BP channel can be reversibly switched between electron- and hole-dominated conductions, resulting in the erased and programmed states exhibiting interchangeable high and low current levels. The BP memory also shows four different memory states and, hence, 2-bit per cell data storage for both n-type and p-type channel conductions, demonstrating the multilevel cell storage capability in a layered material based memory device. The BP memory device with a high mobility and tunable programmed/erased state current ratio and highly reconfigurable device characteristics can offer adaptable memory device properties for many emerging applications in electronics technology, such as neuromorphic computing, data-adaptive energy efficient memory, and dynamically reconfigurable digital circuits.

Characterization of RF Noise in UTBB FD-SOI MOSFET

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.