Back-gate Bias Research Articles

Total Ionizing Dose Responses of Forward Body Bias Ultra-Thin Body and Buried Oxide FD-SOI Transistors

This paper investigates the total ionizing dose (TID) responses of forward body bias (FBB) ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) transistors, which are commonly used in commercial foundries. The experimental results demonstrate that TID-induced threshold voltage shift in FBB nMOSFET cannot be mitigated by applying biasing to back-gate (back-gate biasing). Bias condition dependence has also been explored, revealing that building up of the oxide-trapped charge (Not) in the buried oxide is affected by the electric field induced by the space charge. Moreover, the effect of threshold voltage option on TID responses of UTBB FD-SOI transistors with the undoped channel was first explored. Finally, the TID-enhanced back-gate biasing controlling of the threshold voltage was observed, which is a new phenomenon for the TID responses of UTBB FD-SOI transistors.

Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling

The dopingless tunneling FET (DLTFET) has attracted more and more attention due to the reduction of process complexity comparing to traditional TFET with heavy doping source and drain regions. But the on-state current of conventional DLTFET is lower because its on-state current is only determined by point tunneling (PT) between source and channel. In this work, a new dual-gate DLTFET based on line tunneling (LT) is designed and studied by Sentaurus TCAD simulation tool. The on-state current and subthreshold swing (SS) of DLTFET are greatly improved by skillfully designing back gate engineering and bias. Applying this novel design, the line tunneling is created from channel bottom to channel top, which dramatically enhances tunneling area and tunneling current. So the on-state current of LT_DLTFET consists of point tunneling between source and channel as well as line tunneling in channel region. Comparing to the traditional PT_DLTFET based on Ge, the simulation results reveal that the on-state current of LT_DLTFET based on Ge is increased to 14.8μA/μm from 6.5μA/μm at Vg=1V and Vd=0.5V, and the average SS and minimum SS are decreased to 22.9mV/dec and 6.5mV/dec from 33.9 mV/dec and 9.5mV/dec, respectively. The LT_DLTFET is also proper to both Si and III-V materials. This design greatly promotes the application potential of DLTFET.

A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology

This paper presents a novel low-leakage and high-writable 8T SRAM cell based on FinFET technology. This cell reduces leakage current and consequently leakage power by dynamically adjusting the back gate of the stacked independent-gate FinFET devices. Furthermore, these stacked transistors increase the write static noise margin of the proposed cell due to their role in reducing the strength of the pull-down network of the cross-coupled inverters. The characteristics of this cell are evaluated by device/circuit level simulations using Sentaurus device TCAD device simulator at different supply voltages and in the presence of process variations. The results indicate that the proposed SRAM cell reduces the static power by 37% and 56%, respectively, while providing comparable and even higher static noise margins, as compared to the 6T and 8T FinFET-based SRAM cells.

Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines

In this paper, we present physical insights into the role of substrate on the anomalous frequency behavior of small-signal transconductance and output conductance in the ultrathin body and buried oxide fully depleted silicon-on-insulator MOS transistors. Using the simple dc analysis, we attribute this anomalous behavior to the negative feedback originating from both minority and majority carriers in the substrate at different frequency ranges. Through measurements and detailed TCAD simulations, we have shown that back-gate bias and substrate doping strongly modulate the frequency behavior of transconductance and output conductance. It is finally proposed that circuit/device designers can smartly use the back-gate bias and substrate doping to minimize the substrate effect and improve the frequency response of the device intrinsic gain.

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (WNW) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (WNW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (WNW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec−1 (WNW = 10 nm) to 68 mV dec−1 (WNW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec−1 at the same WNW range, which is a very acceptable results. Additionally, the drain current (ION) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

Effect of gap width on electron transport through quantum point contact in hBN/graphene/hBN in the quantum Hall regime

This study investigates quantized electron transport in high-mobility quantum point contact (QPC) devices in hBN/graphene/hBN in the quantum Hall regime. This study primarily focuses on the effect of the gap width of split gates on edge-channel manipulations, which defines the QPC structure and its electrostatic potential distribution. The quantized conductance is governed by the dynamics of edge channels passing through or backscattered at the QPC, which is controlled by both the top-gate and back-gate biases. The effects of the split-gate gap width and the filling in the QPC on the edge-channel manipulations are experimentally verified. The experimental results are consistent with the theoretical predictions of open/closed configurations of the edge channels around QPC with different gate gap widths.

Dynamic Control of AlGaN/GaN HEMT Characteristics by Implementation of a p-GaN Body-Diode-Based Back-Gate

We report on the implementation of dynamic body-bias technique to improve the performance of AlGaN/GaN high electron mobility transistors (HEMTs) with the successful integration of body-diode. In this configuration, p-GaN body-diode-based back-gate control is used to shift the threshold voltage and dynamically modulate the ON/OFF characteristics of a normally-ON AlGaN/GaN HEMT. A fourth back-gate terminal is connected to the p-GaN layer to control the depletion width of the body-diode, which in turn modulates the 2-D electron gas (2DEG) density. A positive/negative shift in the threshold voltage is measured by increasing/decreasing the depletion width below the channel. A positive back-gate bias application in the ON-state is shown to increase the 2DEG current density resulting in higher ON-current. The application of a negative back-gate bias is shown to be effective in the positive shift of the threshold voltage, in reducing the 2DEG channel current and in increasing the OFF-state break-down voltage. We have experimentally demonstrated enhanced effect of body-diode-based back-gate control in shifting the threshold voltage of a normally-ON HEMT toward normally-OFF mode. The optimum back-gate voltage range which can be applied during both ON and OFF states has been experimentally determined.

Evaluation of Bulk and SOI FeFET Architecture for Non-Volatile Memory Applications

The stress induced by the capping electrode is critical to stabilizing the ferroelectric phase in Si-doped HfO2 which is being actively explored for embedded non-volatile memory applications. While TiN is commonly used as the electrode of choice owing to its thermodynamic stability with HfO2, its work function (WF) (=4.8eV) results in reduced memory window (MW), and higher interlayer field ( $\text{E}_{\mathrm{ IL}}$ ) in bulk Ferroelectric FETs (FeFETs). This is attributed to the built-in electric-field that arises from the WF difference between the metal and the semiconductor. This effectively reduces the ferroelectric hysteresis, and thus, the MW at the read current. Optimizing the MW and the $\text{E}_{\mathrm{ IL}}$ would entail changing the WF, and thus, the capping electrode—essential to retaining the desired ferroelectric properties. We, therefore, propose using the silicon on insulator (SOI)-FeFET architecture which provides an additional knob—back-gate bias ( $\text{V}_{\mathrm{ bg}}$ )—to optimize the MW while reducing the $\text{E}_{\mathrm{ IL}}$ . Further, we show that unlike the bulk FeFET, where a small deviation from the optimal WF dramatically shrinks the MW, the SOI-FeFET facilitates a relatively constant MW over a wide range of $\text{V}_{\mathrm{ bg}}$ . Thus, the SOI-FeFET simplifies the MW & $\text{E}_{\mathrm{ IL}}$ optimization and provides an improved MW versus $\text{E}_{\mathrm{ IL}}$ trade-off in comparison to the bulk FeFET.

Continuous and Reversible Tuning of Electrochemical Reaction Kinetics on Back-Gated 2D Semiconductor Electrodes: Steady-State Analysis Using a Hydrodynamic Method.

Here we report the steady state kinetic analysis of field-effect-controlled outer-sphere electrochemistry on ultrathin back-gated ZnO working electrodes (i.e., 5 nm ZnO electrodes prepared on SiO2/degenerate Si back gates). To achieve steady state conditions in the electrolyte phase, gate-tunable electrochemical flow cells were prepared by integrating a silicone microfluidic channel on the back-gated ZnO electrode. In these flow cells, continuous supply of fresh electrolyte generates time-invariant diffusion layers near the ZnO surface, allowing steady-state kinetic analysis as in other hydrodynamic methods. From the steady-state analysis, it was found that the electron density on the ZnO surface increases with the voltage bias, VBG, applied to the back gate, while the rate constant for electron transfer decreases with VBG. The observed trend can be explained as a result of the field-effect-induced band alignment shift at the ZnO/electrolyte interface which is predicted by our conceptual model; a positive back gate bias shifts the conduction band edge down at a given working electrode potential, leading to an increased surface electron density on ZnO, but simultaneously less overlap of the band edge with the electron acceptor states in solution, which means a lower electron transfer rate constant. Overall, the results quantitatively demonstrate that back gates and the ensuing field effect can be used to control kinetics of interfacial electron transfer at two-dimensional (2D) semiconductor electrodes.

Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at VDD = 0.4 V with high read/write yields.

An SOI Photodetector With Field-Induced Embedded Diode Showing High Responsivity and Tunable Response Spectrum by Backgate

In this paper, we demonstrate experimentally a photodetector based on silicon-on-insulator substrate. The photosensing diode is formed in the substrate induced by the backgate bias instead of doping. TCAD simulation is conducted to confirm that the field-induced junction performs similarly as the doped p-n junction in terms of photodetection. A simplified process flow with low process temperature is developed to fabricate the device, which can save implantation step and reduce the cost. The photoresponses of the device under various biases, light intensities, and wavelengths are studied systematically with both experiment and TCAD simulation. Responsivity up to 1150 A/W is achieved experimentally. In addition, the response spectrum can be modulated by the back gate bias, which is a very attractive feature for multiband photodetection application. The field-induced photodiode in the substrate modulates the threshold voltage of the MOSFET at top Si layer as efficiently as the doped junction, confirmed by TCAD simulation.

Liquid‐Alloy‐Assisted Growth of 2D Ternary Ga2In4S9 toward High‐Performance UV Photodetection

2D ternary systems provide another degree of freedom of tuning physical properties through stoichiometry variation. However, the controllable growth of 2D ternary materials remains a huge challenge that hinders their practical applications. Here, for the first time, by using a gallium/indium liquid alloy as the precursor, the synthesis of high-quality 2D ternary Ga2 In4 S9 flakes of only a few atomic layers thick (≈2.4 nm for the thinnest samples) through chemical vapor deposition is realized. Their UV-light-sensing applications are explored systematically. Photodetectors based on the Ga2 In4 S9 flakes display outstanding UV detection ability (R λ = 111.9 A W-1 , external quantum efficiency = 3.85 × 104 %, and D* = 2.25 × 1011 Jones@360 nm) with a fast response speed (τring ≈ 40 ms and τdecay ≈ 50 ms). In addition, Ga2 In4 S9 -based phototransistors exhibit a responsivity of ≈104 A W-1 @360 nm above the critical back-gate bias of ≈0 V. The use of the liquid alloy for synthesizing ultrathin 2D Ga2 In4 S9 nanostructures may offer great opportunities for designing novel 2D optoelectronic materials to achieve optimal device performance.

Non-Boolean Associative Processing Using FDSOI MOSFET-Based Inverter

Fully depleted silicon-on-insulator (FDSOI) MOSFET-based inverter is used as a distance computing cell (DCC) for non-Boolean associative processing system. Using back-gate bias in FDSOI transistors, the DCC shows excellent controllability of current characteristics of DCC. The system consumes 150 to 300 times lower energy than bulk CMOS-based Boolean implementation and requires lesser number of transistors. It also consumes lower area and energy than most of the other non-Boolean systems. Additionally, output voltage swing, recognition accuracy, and consumed energy in the system, can be controlled by applying proper back gate voltage, on the transistors of winner take all block and DCC.

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits

In this paper, we report on the efforts of applying the dynamic-adjusting threshold-voltage scheme (DATS) to the design of an independent-gate (IG)-mode fin-type field-effect transistor (FinFET) circuit. DATS makes use of the intrinsic advantage of the IG-mode FinFET to adjust the threshold of the front gate with the back-gate bias adaptively according to the operating frequency. Consequently, the power consumption, especially leakage power of the circuit, would be reduced effectively without circuit performance deterioration. By further comparing the circuits where the DATS scheme is employed with the circuits that do not adopt the scheme, the power optimization levels with different path delays in different operating frequency ranges are discussed in detail. A design instance of DATS based on digitally controlled phase-locked loop is implemented with an ASAP 7-nm FinFET model. Simulation results illustrate that by employing DATS the power reduction could be up to 30% in the best case.

Modeling Short-Channel Effects in Asymmetric Junctionless MOSFETs With Underlap

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications.

Regaining Switching by Overcoming Single-Transistor Latch in Ge Junctionless MOSFETs

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing ( ${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs.

The total ionizing dose response of leading-edge FDSOI MOSFETs

In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.

Field-Effect Transistor-Integration with TiO2 Nanoparticles for Sensing of Cardiac Troponin I Biomarker.

The development of electrical biosensor towards device miniaturization in order to achieve better sensitivity with enhanced electrical signal has certain limitations especially complexity in fabrication process and costs. In this paper, an alternative technique with minor modification in the device structure is presented for signal amplification by implementing ambipolar conduction in the biosensor itself. We demonstrated the field-effect transistor (FET)-based biosensor coupled back-gate for attaining a higher sensitivity with the detection of lower target abundance. To utilize the coupled back-gate as a pre-amplifier, silicon-on-insulator wafer with thicknesses of top-silicon and buried oxide (BOX) layers of 70 nm and 145 nm, respectively were desired. Titanium dioxide (TiO2) nanomaterial was deposited using sol-gel method on the channel which acts as a transducer. Surface functionalization on TiO2 thin film allowed an effective immobilization of anti-cardiac troponin I antibody to interact cardiac troponin I (cTnI). Binding events at each step was validated by X-ray photoelectron spectroscopy (XPS) analysis. Further, electrical characterization (Id-Vd) confirms the potentiality of FET-based biosensor to detect cTnI (represents acute myocardial infarction disease) with the concentration ranges from 10 μg/ml down to 1 fg/ml. The sensitivity of 459.2 nA (g/ml)-1 and lower detection limit of 1 fg/ml were achieved at Vbg = -5 V and Vd = 5 V. The designed device demonstrates its ability to detect lower level of cTnI with pre-amplified electrical signal by back-gate biasing.

MoS2 Synaptic Transistor With Tunable Weight Profile

In this paper, bias modulated synapse transistor based on ultrathin molybdenum disulfide (MoS2) was fabricated. By applying positive and negative pulses, the device can imitate the excitation and inhibition behaviors of natural synapse, respectively. The baseline and change percentage of postsynaptic current (PSC) can be tuned by the back-gate bias, enabling the reconfiguration of the weight profile in machine learning. The PSC change tendency between single pulse and multiple pulse tests is opposite, which is very useful to mimic natural synapse recovery feature. Besides, as MoS2 is utilized as channel materials, the device can be vertically scaled down to 2 nm, which is very hard for traditional materials.