Backside Particles Research Articles

Pattern deformation mitigation for EUV photoresists using wafer backside cleaning techniques

This study delves into the effects of wafer backside particles on pattern defocus in EUV lithography (EUVL). Additionally, the potential mitigation of this pattern defocus was examined through wafer backside cleaning. Comparative analyses were conducted between EUVL patterning tests performed using wafers with contaminated and cleaned wafer backside. Defocus points and abnormal critical dimensions (CDs) on the photoresist patterns at the wafer frontside were detected using scanning electron microscopy and optical CD measurement, respectively. The specific locations of these defocus or abnormal CD points were compared and confirmed to be correlated with particles that were present on the same locations on the backside of the wafer. Furthermore, it was found that an effective backside cleaning process can mitigate pattern defocus caused by these wafer backside particles.

Backside wear in total knee replacement: A new quantitative measurement method and a comparison of polished cobalt-chromium tibial trays with titanium tibial trays

Abstract

Backside wear, particle migration and effectiveness of screw hole plugs in acetabular hip joint replacement with cross-linked polyethylene

In total hip arthroplasty, osteolysis of the acetabulum often occurs at the backside of cups in the area of screw holes, indicating a clinically relevant amount of polyethylene (PE) wear particles in this area. In order to avoid a possible migration of wear particles to the acetabulum-bone, screw hole plugs are provided for some implant systems. The aims of this study were to quantitatively determine backside wear and to investigate the migration behaviour of articulation-related wear particles in a cup system with open and closed screw holes by plugs.Titanium cup systems with backside holes for screw fixations were sinusoidally loaded with 2.7 kN. The articulation area was separated from the backside area of the cup. A defined amount of articulation-generated particles was added to the fluid of the articulation chamber. The fluids in the two chambers were separately filtered after 2 × 106 cycles for a particle analysis.Backside wear with noticeably small (65.6 ± 4.2 nm) and round PE particles was identified. With both open and closed screw holes, a migration of the articulating wear particles from the articulation area behind the cup could be observed.Backside wear was estimated to be below 1% of the articulated wear. Screw hole plugs did not effectively prevent the migration of PE wear particles behind the investigated cups. Statement of SignificanceBackside wear occurs in a proven cup-system. Furthermore, it was quantitatively observed that articulation-generated wear products could migrate from the articulating area along the cup/liner-interface through the screw holes behind the cup. An almost unimpeded particle migration to the acetabulum-bone, in conjunction with very small backside wear particles, could produce a clinically relevant amount of PE with respect to pelvic lysis. These findings highlight the importance of management to avoid particle migration in artificial hip cups. Therefore, primarily the use of screw hole plugs, as far as available for the respective cup-system, is recommended. The aim of avoiding particle migration by plugs, but also by using a sophisticated anchoring mechanism between cup and PE liner should continue in future.

Removal of CrN Contamination from EUV Mask Backside Using Dry Cleaning

For EUV lithography, a reflective mask is essential because of use of the strong energy, wavelength of 13.5 nm. The EUV mask consists of multi-layered, multi-material structure and is susceptible to various contaminants. Since EUV lithography process should be used in a high vacuum environment, an electrostatic chuck (ESC) is used to fix or hold the EUV mask using electrostatic force. In general, in order to use ESC chuck, it needs a thin conductive layer (CrN layer) on the backside. However, the contact points of the electrostatic pin chuck can make exfoliation of conductive CrN layer producing CrN particles. If these particles are present on the backside of the mask, CD or DOF may be affected during EUV exposure. The 1 μm particle can leads to a gap radius of 42mm [4]. Moreover, these backside particles may travel to the front side. Therefore, backside cleaning should be performed to remove particles from the mask backside surface.

EUV mask defectivity – a process of increasing control toward HVM

Abstract This article covers the various aspects of defectivity of a typical mask used for extreme ultra-violet (EUV) lithography. The focus of the present article is on those aspects that are more specific for EUV lithography. A prime type of defect that fully falls under the really EUV-specific category consists of the so-called multilayer defects (ML-defects): these defects relate to the ML mirror on the mask, which makes it reflective. While not specific, particle contamination plays a special role in EUV lithography and includes two aspects: both front- and backside of an EUV mask have peculiarities beyond historical deep-UV lithography. Frontside particles can print when they exceed a critical size and, while solvable as in (deep)-UV lithography by means of a pellicle, there are specific challenges. Backside particles can distort a clamped EUV reticle, and the resulting local non-flatness of the reticle may result in focus and overlay errors on the wafer. A last aspect that requires special attention for EUVL can be categorized under reticle degradation by extensive use. That includes the high-volume manufacturing-oriented conditions of high source power needed to obtain competitive throughput. For each aspect of EUV mask defectivity, and hence each type of defect, the paper reviews how the community tackles them and how their possible impact on the result of wafer printing with a given EUV reticle is minimized. This includes a summary of the authors’ own contribution to related learning and developments. Finally, a personal interpretation is given of what are the remaining open items before a workable or full solution can be considered in place.

Middle of Line (MoL) Cleaning Challenges in Sub-20nm Node Device Manufacturing

In advanced technology nodes (sub 20nm), the gate & active contact architecture has become very complex. This architecture not only introduced new materials but also integrated additional patterning mask layers. This necessitated a separate Middle of Line (MoL) zone whereas conventionally contact integration used to be a Front End of Line (FEoL) process. This paper discusses wet cleaning challenges in MoL that were unforeseen with conventional contact architecture. Typical chemistries such as Sulfuric Peroxide Mixture (SPM), dilute Hydrofloric Acid (dHF), Aqua Regia, Standard Clean 1 (SC1), etc. that were used for contact cleaning or in salicidization process are found to be too aggressive due to smaller process window, shrinking Critical Dimensions (CD), and other challenges arising from overall tighter tolerances. As a result of device scaling, most of the MoL mask patterning is done with immersion lithography and double patterning techniques such as Litho-Etch Litho-Etch (LELE) are also needed. Immersion lithography is very sensitive to pre-litho backside and frontside particles which make pre-litho cleaning in MoL very critical as well. Also due to lack of high aspect ratio features in MoL (mostly contact holes), physical particle removal techniques such as droplet spray and MegaSonic can be very effectively used to achieve higher Particle Removal Efficiency (PRE). This paper summarizes such different scenarios & related challenges.

Removing Organic Residues Using Backside Brush Scrubber Clean

Cleaning is an important part of advanced semiconductor manufacturing process. As the technology node advances, it has become more and more challenging. In 2X nm devices, excursions of organic residues are detected on the product wafers. These clusters of organic residues are found to be die killers and hence, reduce the yield of the product. In this work, we will focus on root cause finding for the organic residue clusters and the proposed solution. Defectivity, electrical, and yield data are presented to show the effectiveness of the proposed solution. Figure 1 shows defectivity improvement of 11X as compared to the current integration scheme. Figure 2 is typical example of organic residues and cluster on wafers. Figure 3 shows the comparison of chemistries applied. Figure 4 demonstrates the product yield improvement of 3.1% after the introduction of the proposed solution. References H.-S. Sohn et.al Removal of Backside Particles by Single Wafer Magasonic Systems, ECS transactions, 11(2) 95-100 (2007)Antoine Pacco et.al Focus Spot Reduction by Brush Scrubber Cleaning, Solid State Pheonomena Vol 219, 276-279 (2015) Figure 1

Simultaneous Removal of Particles from Front and Back Sides by a Single Wafer Backside Megasonic System

In IC manufacturing, particle removal from a wafer's back side (BS) has become as important as that from the front side (FS). For example, during lithography, BS particles can cause a variation on the topside surface topography. This may result in a focus-spot failure due to the reduced process window for depth of focus (DOF) as shown in Fig. 1. This problem increases as the feature size decreases. BS particles may cause other problems in wet benches, where BS particles can be transferred to the adjacent front side of wafers. Fig. 2 shows these FS particles, which usually appear as flow or streak patterns on the wafer [.

Using Ionizers to Reduce Electrostatically Adhered Particles on Wafer Backside

We present results and discussion on the positive impact of ionizer(s) used in multiple configurations on wafer backside and front-side particle adders in physical vapor deposition (PVD) processing tools. We provide a hypothesis, followed by testing, that establishes a relationship between electrical surface charge collection data and particle data obtained in a laboratory setting as well as a real-world wafer fabrication facility environment. For chip manufacturers, controlling surface charges on production wafers results in a reduced number of undesirable particles, thereby resulting in higher yield, more reliable final product chips, and reduced product losses. And for equipment manufacturers, more reliable and better tool performance can lead to increased productivity. The INOVA PVD system's good particle performance, as demonstrated on good quality wafers, is made marginal quality wafersmore robust with an ionizer installation when marginal quality wafers are used.

Wafer Backside Particle Reduction By Optimizing AC3 Coating for Poly Etch Chamber

As semiconductor devices are being scaled down to CD (Critical Dimension) of 65nm and below, the control of chamber condition in Poly Etch chamber is critical to achieve stable CD and defect performance from wafer to wafer, lot to lot. AC3 (Advanced Chamber Condition Control) coating is widely used after traditional WAC (Waferless Auto Clean): an SiCl4 coating step is added after WAC to coat a thin layer on both chamber wall and ESC chuck. This layer maintains chamber in good condition for every wafer to achieve stable Etch Rate, CD and defect performance, while low quality coating makes wafer backside particle high. This paper introduces two key factors for SiCl4 coating quality control which affects wafer backside particle performance. One is SiCl4 gas overshoot, the other one is ESC temperature effect. The wafer backside particle high can finally cause wafer frontside high defect count.

Removal of Backside Particles by a Single Wafer Megasonic System

Single wafer megasonics were used to remove backside particle contamination resulting from vacuum chucks and chambers. Process evaluation was done using blanket wafer experiments with Si3N4 particles. To increase the difficulty of the particle removal test vehicle, aged contaminated wafers were used. The impact of film type, megasonic power, process chemicals and etch amount were investigated. The impact of performing a backside megasonic clean prior to the lithography process was shown

Removal of Backside Particles by a Single Wafer Megasonic System

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Direct Focused Ion Beam Drilling of Nanopores

AbstractFocused 30keV gallium ion beam, single-pixel drilling combined with backside particle detection is used to fabricate pores having exit diameters as small as ~11 nm in 200 nm-thick silicon nitride membranes. The backside channelplate detector response obtained about the onset of breakthrough is interpreted by plan-view transmission electron microscopy investigations of hole morphology. Immediately prior to breakthrough, there is a rise in detector signal as the local membrane thickness is reduced. This likely occurs as a result of ion transmission and, possibly, forward sputtering. At the dose required for breakthrough a maximum detector signal is obtained thus providing a potential method for end point detection. The focused ion drilling technique avoids broad area beam exposure methods that are often used to reduce hole diameter to nanometer dimension. In addition, the current approach overcomes difficulties in determining a required dose for breakthrough such as those that arise from an inhomogeneous membrane thickness, redeposition, or ion channeling.

The Effect of Backside Particles on Substrate Topography

The presence of a particle on the backside of a wafer is commonly acknowledged to produce a deflection of the wafer when it is held on a flat surface by means of a pressure difference. We simulated this wafer topography, taking into account both elastic and plastic deformations. The simulations are backed up by experimental evidence. The results show that height variations of 100 nm can extend over several mm. At the same time, indentation and plastic deformation reduce the surface height variations to values that are orders of magnitude below those predicted in the ITRS roadmap.

The Impact of Backside Particles on the Limits of Optical Lithography

The Impact of Backside Particles on the Limits of Optical Lithography

Compliant pin chuck for minimizing the effect of backside particles on wafer planarity

A wafer chuck referred to as the compliant pin chuck (CPC) that can minimize the nonplanarity effect of backside particles on semiconductor wafers is presented in this article. The demand for flatter semiconductor substrates has been increasing as the size of the features that can be transferred onto a wafer surface becomes smaller. There are a number of factors affecting wafer planarity, most of which can be corrected by conventional wafer chucks. However, the problem of backside particles (particles affect a large portion of wafer real estate by causing out-of-plane distortion when they get lodged between a wafer and a wafer chuck) has not been adequately addressed by the current wafer chuck technology. The compliant pin chuck was designed to address this concern and fabricated from silicon using lithography based microfabrication techniques. The chuck consists of an array of microflexure mechanisms that react to the presence of backside particles so as to minimize the nonplanarity caused otherwise. It is also shown through experimental results that the fabricated chuck has a planarity of 120nm (standard deviation −3σ) over an area of 30mm×30mm and is less sensitive to backside particles than a conventional wafer chuck.

Three hundred-mm wafers: a technological and an economical challenge

For the transition from 200- to 300-mm wafers, in addition to the technological challenges, there is the equivalent cost challenge to be met. The ultimate target is cost parity per unit area of silicon between 200 and 300 mm. The major blocking point to be cleared appears to be crystal pulling. The question of cost of crystal pulling is mainly related to the large crystal weights (>300 kg) and to the issue of crystal defects (crystal originated pits (COPs); voids in the Si crystal) generated by crystal pulling. An alternative route to address the defect problem is to use epitaxy to create a defect-free layer of Si for the active device regions. Close co-operation between wafer manufacturers and users is absolutely necessary to address these key issues. Furthermore, to contain cost, wafer makers and device manufacturers have to work together intensively to implement standardisation wherever possible and to avoid cost driving overspecifications (e.g. for front and backside particles or flatness).