Three hundred-mm wafers: a technological and an economical challenge

Abstract

For the transition from 200- to 300-mm wafers, in addition to the technological challenges, there is the equivalent cost challenge to be met. The ultimate target is cost parity per unit area of silicon between 200 and 300 mm. The major blocking point to be cleared appears to be crystal pulling. The question of cost of crystal pulling is mainly related to the large crystal weights (>300 kg) and to the issue of crystal defects (crystal originated pits (COPs); voids in the Si crystal) generated by crystal pulling. An alternative route to address the defect problem is to use epitaxy to create a defect-free layer of Si for the active device regions. Close co-operation between wafer manufacturers and users is absolutely necessary to address these key issues. Furthermore, to contain cost, wafer makers and device manufacturers have to work together intensively to implement standardisation wherever possible and to avoid cost driving overspecifications (e.g. for front and backside particles or flatness).