Abstract
As semiconductor devices are being scaled down to CD (Critical Dimension) of 65nm and below, the control of chamber condition in Poly Etch chamber is critical to achieve stable CD and defect performance from wafer to wafer, lot to lot. AC3 (Advanced Chamber Condition Control) coating is widely used after traditional WAC (Waferless Auto Clean): an SiCl4 coating step is added after WAC to coat a thin layer on both chamber wall and ESC chuck. This layer maintains chamber in good condition for every wafer to achieve stable Etch Rate, CD and defect performance, while low quality coating makes wafer backside particle high. This paper introduces two key factors for SiCl4 coating quality control which affects wafer backside particle performance. One is SiCl4 gas overshoot, the other one is ESC temperature effect. The wafer backside particle high can finally cause wafer frontside high defect count.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
