Asymmetric Underlap Research Articles

High-Performance Exploration of Buried Channel In0.53Ga0.47/InP Stepped Poly Gate MOSFET Using Asymmetric Underlap Gate Spacer

In recent times the double gate In0.53Ga0.47As/InP heterostructure MOSFET offers excellent electrostatic/RF performance in comparison with conventional Si-bulk MOSFET. Drain capacitance of DG-MOSFETs are mostly dominated by overlap capacitance due to the reduction junction capacitance and this can be minimized by inserting an underlap area between the source and drain region. Further, source side underlap contributes substantial deterioration of On current and increased threshold voltage variation. So, to overcome this problem, a high K spacer is introduced in the drain side of the gate region which reduces the parasitic capacitance without hampering the On current. This works investigates the impact of drain side spacer underlap on stepped poly gate In0.53Ga0.47As/InP asymmetric heterostructure (ASSH) double-gate (DG) MOSFET to improve the device performance. In the proposed model the poly gate splits into three steps with an expansion of gate oxide width from the source region to the drain region. So ASSH-DG MOSFET exhibits the exceptional benefits mainly owing to, (a) the reduced oxide thickness at the source, which results in a good electrostatic gate control along the channel, (b) the larger oxide thickness near the drain lowering the gate-to-drain capacitance, henceforth there is an improvement of On resistance in the linear region. The device performance metrics are examined using a 2D TCAD device simulator by considering the underlap length ranging from 0 nm to 8 nm with a step of 2 nm. Simulated results show ASSH-DG MOSFET exhibits a significant improvement of analog /RF parameters as compared to conventional hetero (H)-DG MOSFET.

Enhanced logic gates and SRAM based on reconfigurable field-effect transistor with asymmetric spacer engineering

In this paper, an early evaluation of reconfigurable field-effect transistor (RFET) with asymmetric spacer engineering in terms of logic cells and static random-access memory (SRAM) is carried out using 3D-TCAD and logical effort theory. The asymmetric underlap channel extension at the drain side (UCED) is demonstrated to be able to increase the on-state saturated current (I ON). Furthermore, the proposed UCED RFET shows great stability for different spacer materials, compared to the conventional RFET. Though a slight deterioration of the normalized delay in UCED RFET, the propagation delay of UCED structure is still smaller due to the lower intrinsic delay in the transistor level because control gate capacitance reduces in the meantime. RFET with asymmetric spacer engineering is also demonstrated to relax the competition between the read and the write operation in SRAM.

Novel Reconfigurable Field-Effect Transistor With Asymmetric Spacer Engineering at Drain Side

In this article, a novel reconfigurable field-effect transistor with an asymmetric underlap channel extension at drain side (UCED-RFET) is proposed for the first time. The influence of underlap extension is investigated by extensive 3-D device simulation. Results show that compared to the conventional RFET with symmetrical underlap-channel extension at source and drain end, the ON-state saturated current ( ${I}_{ \mathrm{ON}}$ ) of our proposed UCED-RFET is greatly increased without degenerating the OFF-state leakage current ( ${I}_{ \mathrm{OFF}}$ ), and the ratio of ${I}_{ \mathrm{ON}}/{I}_{ \mathrm{OFF}}$ is up to 109. The underlying physical mechanism is explored and the enhanced gate coupling is demonstrated to contribute to the improved performance in our proposed UCED-RFET. Moreover, the effects of gate dielectric materials and different spacers are investigated, and the results correlated with the scaling properties are also reported.

Analysis of low frequency noise for asymmetric underlap UTB SOI MOSFETs

Analysis of low frequency noise for asymmetric underlap UTB SOI MOSFETs

Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers

Using well-calibrated device simulation, the analogue performance of 20 nm double-gate junctionless transistors (JLTs) is investigated in terms of transconductance (g m), output conductance (g d) for various underlap spacer asymmetricity and dielectric constant (k) values. The spacer length is varied ranging 1–6 nm on both source (L S) and drain sides (L D) while keeping their sum fixed at 12 nm. Obtained results show that for both n- and p-metal-oxide-semiconductor field-effect transistors (FETs), a longer LD increases gm exhibiting weak sensitivity to variations in k while gd increases and decreases with higher and lower k. The present findings reveal that the highest voltage gain of 46.3 and largest gain bandwidth (GBW) of 676 GHz are obtained for complementary metal–oxide–semiconductor (CMOS) amplifiers featuring both n and p transistors with L S = 11 nm, L D = 1 nm and k = 80 and L S = 1 nm, L D = 11 nm and k = 3.9; both figures are quite higher compared with their symmetric counterpart. The studies manifest that such an asymmetric dielectric spacer engineering could be employed in designing high performance nanoscale CMOS amplifiers without increasing hardly any process complexity and cost while providing augmented GBW compared with reported amplifiers based on molybdenum disulphide transistors and tunnel FETs.

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length LED of 10 nm and source-side spacer length LES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain Av, unity-gain cut-off frequency fT and maximum frequency of oscillations fMAX by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak Av while decreasing both peak fT and fMAX. The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at LED = 10 nm with a SiO2 spacer.

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in I on /I off and reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm FinFETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation.

High-Performance Asymmetric Underlap Ge-pTFET With Pocket Implantation

This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current ( $I_{\mathrm{\scriptscriptstyle OFF}})$ of 50-nm Ge-pTFETs to about 3.27 pA/ $\mu \text{m}$ without degrading the ON-current ( $I_{\mathrm{\scriptscriptstyle ON}})$ , and a p+ pocket doping improves the ion of these devices to about 0.295 mA/ $\mu \text{m}$ without compromising $I_{\mathrm{\scriptscriptstyle OFF}}$ . The analog and RF performances of the drain-underlapped Ge-pTFETs are investigated in terms of the drain current, transconductance, output resistance, intrinsic gain, cutoff frequency, and maximum frequency of oscillation for pocket-doping length varying from 0 to 6 nm. In addition, the influence of the pocket doping on the nonquasi-static performance is analyzed in terms of the gate–source and gate–drain capacitances, gate–drain resistance, and intrinsic delay time. Finally, the performance of the source-pocket drain-underlapped Ge-pTFETs in ICs is studied using a common source amplifier.

Benefits of asymmetric underlap dual‐ k spacer hybrid fin field‐effect transistor over bulk fin field‐effect transistor

Asymmetric underlap dual-k spacer hybrid fin field-effect transistor (FinFET) is a novel hybrid device that combines three significant and advanced technologies, i.e. ultra-thin body, three-dimensional (3D) FinFET, and asymmetric spacer engineering on a single silicon on insulator platform. This innovative architecture promises to enhance the device performance as compared with conventional FinFET without increasing the chip area. Recently, high-k dielectric spacer materials are of research interest due to their better electrostatic control and more immune towards short channel effects in nanoscale devices. For the first time, this study introduces an asymmetric high-k dielectric spacer near the source side with optimised length in hybrid FinFET and claims an improvement in device integrity. From extensive 3D device simulation, the authors have determined that the proposed architecture is superior in performance as compared with traditional FinFET.

Physical Insights Into Electric Field Modulation in Dual-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula> Spacer Asymmetric Underlap FinFET

In this paper, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed. The significance of using dual-k spacers is illustrated considering the parasitic outer fringing capacitance. The study also presents physical insights into inversion charge modulation by dual-k spacers in DKAU-FinFETs. In addition, the proposed device structure is analyzed for analog, RF, and digital circuit performances. Based on the performance analysis, the use of optimum inner high-k spacer thickness is proposed for reliable device performance.

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches.

Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications

Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications

Analysis of High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Spacer Asymmetric Underlap DG-MOSFET for SOC Application

In this paper, asymmetric underlap double-gate (AUDG) MOSFET is studied to analyze the influence of high- $k$ spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high- $k$ spacers. To evaluate the device performance and to study the improvement associated with the use of high- $k$ spacers, different intrinsic parameters are analyzed. These parameters include transconductance ( $g_{m})$ , transconductance generation factor ( $g_{m}$ / $I_{d})$ , intrinsic gain ( $g_{m}r_{o})$ , intrinsic capacitance ( $C_{\rm gd}$ , $C_{\rm gs})$ , resistance ( $R_{\rm gd}$ , $R_{\rm gs})$ , transport delay ( $\tau _{m})$ , inductance ( $L_{\rm sd})$ , cutoff frequency ( $f_{T}\!)$ , and the maximum frequency of oscillation ( $f_{\rm {max}})$ , gain bandwidth product, and inverter delay.

Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs

This paper presents a systematic study of the effect of source/drain (S/D) implant lateral straggle on the RF performance of the symmetric and asymmetric underlap double gate (UDG) MOSFET devices. The length of the underlap regions ( L \({}_{un}\) ) on each side of the gate is a critical technology parameter in determining the performance of UDG-MOSFETs. However, the value of L \({}_{un}\) is susceptible to variation due to S/D implant lateral diffusion. Therefore, it is critical to investigate the impact of S/D implant lateral straggle on the performance of UDG-MOSFETs. This paper shows that the improvement in the RF performance of the UDG-MOSFETs over the conventional DG-MOSFETs can be achieved by optimizing the S/D lateral straggle of the asymmetric UDG-MOSFETs. The RF performance study includes intrinsic capacitances and resistances, transport delay, inductance, and the cut-off frequency.

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.

Asymmetric Underlap in Scaled Floating Body Cell Memories

The asymmetric underlap device for a floating body cell is proposed without any extra process or photomask during fabrication. The electric field in the gate-drain underlap region is quietly relaxed. It is found that memory operation would fail in bipolar-based floating body cells because band-to-band tunneling significantly alters the body potential. Measurements show the proposed structure could indeed suppress the undesirable band-to-band tunneling greatly so that the bistable state via the parasitic bipolar junction transistor is ensured in scaled floating body cells. The parasitic capacitances in both word line and bit line are also reduced.

Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation

In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D Poisson's equation is obtained with approximation of parabolic potential function along vertical direction of the device. Conformal mapping technique is applied for modeling fringe electric field in the underlap regions. The proposed potential model is extended in deriving important device parameters such as threshold voltage, threshold voltage rolloff, DIBL, subthreshold swing, etc. Model predictions demonstrate that significant improvement in subthreshold operation can be achieved with 4T asymmetric underlap DG MOSFETs in comparison to 3T symmetric nonunderlap DG MOSFETs.

Gate Underlap Design for Short Channel Effects Control in Cylindrical Gate-all-around MOSFETs based on an Analytical Model

Gate underlap structure can be utilized to improve the immunity to short channel effects in MOSFET devices. In this work, gate underlap design scheme in cylindrical gate-all-around MOSFETs is explored based on an analytical model. This model takes into account the fringing field from gate electrode to underlap regions based on conformal mapping and a channel length transformation method. By solving Poisson equations in the underlap and channel regions and matching the boundary conditions, this model reproduces the channel potential profile in subthreshold operation region. Both symmetric and asymmetric underlap structures are covered. The developed model is verified extensively with TCAD simulations. A gate underlap design scheme is then provided based on this analytical model.