High-Performance Asymmetric Underlap Ge-pTFET With Pocket Implantation

Abstract

This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current ( $I_{\mathrm{\scriptscriptstyle OFF}})$ of 50-nm Ge-pTFETs to about 3.27 pA/ $\mu \text{m}$ without degrading the ON-current ( $I_{\mathrm{\scriptscriptstyle ON}})$ , and a p+ pocket doping improves the ion of these devices to about 0.295 mA/ $\mu \text{m}$ without compromising $I_{\mathrm{\scriptscriptstyle OFF}}$ . The analog and RF performances of the drain-underlapped Ge-pTFETs are investigated in terms of the drain current, transconductance, output resistance, intrinsic gain, cutoff frequency, and maximum frequency of oscillation for pocket-doping length varying from 0 to 6 nm. In addition, the influence of the pocket doping on the nonquasi-static performance is analyzed in terms of the gate–source and gate–drain capacitances, gate–drain resistance, and intrinsic delay time. Finally, the performance of the source-pocket drain-underlapped Ge-pTFETs in ICs is studied using a common source amplifier.