Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers

Abstract

Using well-calibrated device simulation, the analogue performance of 20 nm double-gate junctionless transistors (JLTs) is investigated in terms of transconductance (g m), output conductance (g d) for various underlap spacer asymmetricity and dielectric constant (k) values. The spacer length is varied ranging 1–6 nm on both source (L S) and drain sides (L D) while keeping their sum fixed at 12 nm. Obtained results show that for both n- and p-metal-oxide-semiconductor field-effect transistors (FETs), a longer LD increases gm exhibiting weak sensitivity to variations in k while gd increases and decreases with higher and lower k. The present findings reveal that the highest voltage gain of 46.3 and largest gain bandwidth (GBW) of 676 GHz are obtained for complementary metal–oxide–semiconductor (CMOS) amplifiers featuring both n and p transistors with L S = 11 nm, L D = 1 nm and k = 80 and L S = 1 nm, L D = 11 nm and k = 3.9; both figures are quite higher compared with their symmetric counterpart. The studies manifest that such an asymmetric dielectric spacer engineering could be employed in designing high performance nanoscale CMOS amplifiers without increasing hardly any process complexity and cost while providing augmented GBW compared with reported amplifiers based on molybdenum disulphide transistors and tunnel FETs.