High-Performance Exploration of Buried Channel In0.53Ga0.47/InP Stepped Poly Gate MOSFET Using Asymmetric Underlap Gate Spacer

Abstract

In recent times the double gate In0.53Ga0.47As/InP heterostructure MOSFET offers excellent electrostatic/RF performance in comparison with conventional Si-bulk MOSFET. Drain capacitance of DG-MOSFETs are mostly dominated by overlap capacitance due to the reduction junction capacitance and this can be minimized by inserting an underlap area between the source and drain region. Further, source side underlap contributes substantial deterioration of On current and increased threshold voltage variation. So, to overcome this problem, a high K spacer is introduced in the drain side of the gate region which reduces the parasitic capacitance without hampering the On current. This works investigates the impact of drain side spacer underlap on stepped poly gate In0.53Ga0.47As/InP asymmetric heterostructure (ASSH) double-gate (DG) MOSFET to improve the device performance. In the proposed model the poly gate splits into three steps with an expansion of gate oxide width from the source region to the drain region. So ASSH-DG MOSFET exhibits the exceptional benefits mainly owing to, (a) the reduced oxide thickness at the source, which results in a good electrostatic gate control along the channel, (b) the larger oxide thickness near the drain lowering the gate-to-drain capacitance, henceforth there is an improvement of On resistance in the linear region. The device performance metrics are examined using a 2D TCAD device simulator by considering the underlap length ranging from 0 nm to 8 nm with a step of 2 nm. Simulated results show ASSH-DG MOSFET exhibits a significant improvement of analog /RF parameters as compared to conventional hetero (H)-DG MOSFET.