Radiation Effects in VLSI Circuits - Part II: Hardening Techniques

Abstract

This work presents a comprehensive review on radiation hardening techniques aimed at enhancing the resilience of VLSI circuits against soft errors. The study covers a wide approaches for both technological and design-based strategies. Process hardening, shielding, guard rings, silicon on insulator, enclosed layout transistor, masking and transistor sizing are explored to mitigate the impact of radiation-induced errors on VLSI circuit behavior. Furthermore, the paper delves into more advanced methodologies, including TMR, error correction codes, logic duplication, and the integration of guard cells. These techniques offer varying levels of protection against soft errors. The review critically examines the strengths, limitations, and trade-offs associated with each approach, highlighting their suitability for radiation environments. The primary objective of this research is to provide a comprehensive overview of the radiation hardening techniques, which facilitate to understand principles of practical implementations. This review work offers value for VLSI circuit designers and researchers who intend to make electronic systems more reliable in the presence of radiation-induced soft errors with technological and design-oriented approaches. To highlight understanding, we have ended most of the sections and subsections with questions. These questions can help researchers explore related research directions.