Approximate Multipliers Research Articles

Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm

Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm

PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier With Unbiasedness and Configurability

Approximate computing is a promising alternative to improve energy efficiency for IoT devices on the edge. This work proposes a piecewise-linearly-approximated and unbiased floating-point approximate multiplier with run-time configurability. We provide a theoretically sound formulation that turns multiplication approximation to an optimization problem. With the formulation and findings, a multi-level architecture is proposed to easily incorporate run-time configurability and module execution parallelism. Finally, the proposed multiplier is further optimized to reduce the circuit implementation complexity, making the multiplier linearly dependent on the precision requirement, instead of quadratically or exponentially as in prior work. When compared to the prior state-of-the-art approximate floating-point multiplier, ApproxLP M. Imani <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al</i> , “ApproxLP: Approximate multiplication with linearization and iterative error control,” in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Proc. ACM/IEEE Des. Autom. Conf.</i> , 2019, pp. 1–6., the proposed multiplier outperforms in all the aspects including accuracy, area, and delay. By replacing a full-precision floating-point multiplier in GPU, the proposed design can improve the energy efficiency for various edge computing tasks. Even with Level 1 approximation, the proposed multiplier improves energy efficiency up to 20× for machine learning on CIFAR-10, with almost negligible accuracy loss.

Design of Power and Area Efficient Approximate Multipliers for Edge Detection Algorithm

Abstract: In this paper, we present a novel approximate computing scheme suitable for realizing the energy-efficient multiplyaccumulate (MAC) processing. First we design the approximate 4-2 compressors generating errors in the opposite direction while minimizing the computational costs. Based on the probabilistic analysis, positive and negative multipliers are then carefully developed to provide a similar error distance. Simulation results on various practical applications reveal that the proposed MAC processing offers the energy-efficient computing scenario by extending the range of approximate parts. This Design is implemented by Verilog HDL and simulated by Modelsim 6.4 c. The Performance is measured by Xilinx tool Synthesis Process. The proposed Sobel edge detection algorithm uses approximation methods to replace the complex operations; This design is done by Matlab and Modelsim using hdldameon, This proposed multipliers arerpelaced in the sobel operator based image Edge detection.

Designing Energy-Efficient Approximate Multipliers

This paper proposes a novel approach suitable to design energy-efficient approximate multipliers using both ASIC and FPGAs. The new strategy harnesses specific encoding logics based on bit significance and computes the approximate product performing accurate sub-multiplications by applying an unconventional approach instead of using approximate computational modules implementing traditional static or dynamic bit-truncation approaches. The proposed platform-independent architecture exhibits an energy saving of up to 80% over the accurate counterparts and significantly better behavior in terms of accuracy loss with respect to competitor approximate architectures. When employed in 2D digital filters and edge detectors, the novel approximate multipliers lead to an energy consumption up to ~82% lower than the accurate counterparts, which is up to ~2 times higher than that obtained by state-of-the-art competitors.

ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis

Approximate computing is a promising approach to the design of area–power-performance-efficient circuits for computation error-tolerant applications such as image processing and machine learning. Approximate functional units, such as approximate adders and approximate multipliers, have been actively studied for the past decade, and some of these approximate functional units can dynamically change the degree of computation accuracy. The greater their computational inaccuracy, the faster they are. This study examined the high-level synthesis of approximate circuits that take advantage of such accuracy-controllable functional units. Scheduling methods based on integer linear programming (ILP) and list scheduling were proposed. Under resource and time constraints, the proposed method tries to minimize the computation error of the output value by selectively multi-cycling operations. Operations that have a large impact on the output accuracy are multi-cycled to perform exact computing, whereas operations with a small impact on the accuracy are assigned a single cycle for approximate computing. In the experiments, we explored the trade-off between performance, hardware cost, and accuracy to demonstrate the effectiveness of this work.

Smart Trolley Application with an Approximate Multiplier Approach Using Embedded Platform

Shopping malls, these days, are crowded and many people find it time-consuming and hard to shop. Locating a commodity coupled with standing in long queues for billing looks cumbersome. To overcome these difficulties, the authors of this paper, present the design of the product, smart trolley. When the customer enters the market, he has to log-in to the product and the map of the supermarket is displayed on the LCD screen. Later, once he starts shopping, upon entering each aisle, the details of the products in the aisle are displayed. For billing, the user has to scan the bar code for packed goods and based on the scanned code corresponding to the product, the price is displayed. For unpacked items such as fruits, vegetables etc, a picture of the commodity is taken which is classified with neural networks, the weight of the commodity is measured and the price is calculated with this information. Later, the customer has to click the finish button upon finishing shopping and pay via online transactions. This system design is validated with a prototype that has a camera, transducers, LCD screens RFID readers and raspberry Pi embedded in it. RFID technology is used for location tracking, cameras are used for scanning bar codes (packed goods) and taking snaps of commodities (unpacked) and a force transducer is used for measuring weight. Finally, the database images are multiplied with different level of approximate multipliers and various error level database has been created. The accuracy of all databases is tested with the VGG-16 network.

Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing

Multiply and accumulate (MAC) composed of a set of multipliers and one reduction dominates the latency and power of convolutional neural network (CNN) accelerators. Existing approximate multipliers reduce latency and power at a tolerable drop in accuracy, without considering the data distribution (implicitly assuming that data are uniformly distributed). This letter discloses that practical CNNs’ activations and weights are usually Gaussian-like distributed, and the bits of quantized activations and weights are typically not with a probability of 0.5. Thus, we propose an approximate MAC unit design by taking into account the statistical features of input data, to achieve a balanced tradeoff among latency, power, and accuracy. The extensive experiments show that our proposed MAC unit design provides much higher accuracy than state-of-the-art approximate circuits, while the latency, area, and power are similar.

A Hardware- and Accuracy-Efficient Approximate Multiplier with Error Compensation for Neural Network and Image Processing Applications

A Hardware- and Accuracy-Efficient Approximate Multiplier with Error Compensation for Neural Network and Image Processing Applications

Design and FPGA Implementation of High Throughput and Low Latency Machine Learning based Approximate Multiplier for Image Processing Applications

One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.

Approximate Recursive Multipliers Using Low Power Building Blocks

Approximate computing, frequently used in error tolerant applications, aims to achieve higher circuit performances by allowing the possibility of inaccurate results, rather than guaranteeing a correct outcome. Many contributions target the binary multiplier aiming to minimize the complexity of this common yet power-hungry circuit. Approximate recursive multipliers are low-power designs that exploit approximate building blocks to scale up to their final size. In this paper, we present two novel 4×4 approximate multipliers obtained by carry manipulation. They are used to compose 8×8 designs with different error-performance trade-off. The final circuits exhibit a competitive behavior in terms of error while reducing the power dissipation when compared to state-of-the-art proposals. The proposed multipliers and state-of-the-art designs found in the literature, have been synthesized targeting a 14nm FinFET technology to determine the electrical characteristics. Compared with an exact 8×8 multiplier, the least dissipative design proposed in this paper reduces power consumption and silicon area by 46%, and minimum delay by 21%. It also consumes 14% less power than the least power-hungry recursive circuit found in the literature, while offering 81% higher accuracy. Ιmage processing applications and a convolutional neural network are shown to demonstrate the effectiveness of the proposed multipliers.

Design and Analysis of Approximate 4-2 Compressor for Efficient Multiplication

Approximation computing concepts have been introduced and studied to provide sufficient accuracy with low power. Many approximate 4-2 compressor designs and methods are proposed to build approximate multipliers. However, most of the designs used for conventional approximate multipliers have been proposed to achieve low power by compromising accuracy or to maintain accuracy with low performance. In this study, a new 4-2 compressor is proposed to improve the error rate, delay, and power consumption. The proposed compressor was used to build an approximate multiplier. Transistor-level SPICE simulations with a high-performance 32-nm predictive technology model (PTM) were conducted to verify the efficiency of the proposed design. The results show that the proposed 4-2 compressor design can achieve up to 4.2% and 22.5% improvement in power consumption and delay, respectively. The proposed multiplier design can achieve up to 4.2% and 15.5% improvement in power consumption and error metrics, respectively. Compared to other designs, the proposed multiplier has lower error in small operand operations.

The Hardware Cost and Computing Accuracy Trade-off in Multipliers using Imprecise 4-2 Compressors for Image Processing Applications

Approximate computing has been widely used in image processing applications to significantly reduce the hardware cost of circuits; however, this induces a sacrifice in computing accuracy. The compromise between accuracy and hardware cost in approximate multipliers has not been investigated yet. To address this issue, this paper proposes a set of approximate 8×8 Dadda multipliers built by using an efficient imprecise 4-2 compressor. The compressor introduces symmetrical errors into the truth table of the exact design to reach a simpler structure. Furthermore, as an important image processing application, image multiplication is implemented with the proposed multipliers. Synthesis and simulation results show that the overall performance of the multipliers varies depending on the various assessment criteria. Utilization of the modified compressor in the multipliers results in area, delay, and power reductions of 38%-72%, 14%-33%, and 39%-77%, respectively, compared to the exact design, while maintaining acceptable computing accuracy in image multiplication. According to the results, the proposed multipliers achieve a better trade-off between energy efficacy and computing accuracy than the existing designs, which could be certified as options for exact multipliers in image processing.

Low-power and high-speed approximate multiplier using higher order compressors for measurement systems

At present, approximate multipliers are used in the image processing applications. These approximate multipliers are designed with the help of higher order compressors to decrease the number of addition stages involved for the lessening stages. The approximate computing is the best technique to improve the power efficiency and reduce delay path. With the use of approximate computing multiple compressors are designed. In this paper, 10:2 compressors are designed and implemented in the 32-bit multiplier and compared with the exact 32-bit multipliers. The proposed higher bit compressors along with the lower bit compressors are implemented to reduce the delay of the design. This type of digital circuits has much significance in measurement technologies, for enabling fast and accurate measurements. With the use of approximate compressors, the result may be ineffective, but the power consumption and delay are getting reduced. Hence, these proposed multipliers are only implemented the digital signal processing applications, where there is need for combining two or more signals. The proposed multiplier is used for implementing FIR filter resulted 27 ns delay which is far better than the exact multiplier having 119 ns. These multipliers also used in image processing applications and PSNR of image has been employed.

A modified truncation and rounding-based scalable approximate multiplier with minimum error measurement

&lt;p&gt;Multiplication necessitates more hardware resources and processing time. In a scalable method of approximate multiplier, the truncated rounding technique is added to reduce the number of logic gates in partial products with the help of leading one-bit architecture. Truncation and Rounding based Scalable Approximate Multiplier (TOSAM) has few modes of error measurement based upon height (h) and truncated (t) named as (h,t). These multipliers are named as TOSAM(0,2), TOSAM(0,3), TOSAM(1,5), TOSAM(2,6), TOSAM(3,7), TOSAM(4,8), and TOSAM(5,9). Multiplication provides a substantial impact on metrics like power dissipation, speed, size and power consumption. A modified approximate absolute unit is proposed to enhance the performance of the existing approximate multiplier. The existing 16-bit (3,7) error measurement multiplier shows an error measurement value of 0.4 %. The proposed 16-bit multiplier for the same error measurement possesses the error measured value is of 0.01%, mean relative error measured value of 0.3 %, mean absolute relative error measured value of 1.05, normalized error distance measured value of 0.0027, variance of absolute error measured value of 0.52, delay of 1.87 ns, power of 0.23 mW, energy of 0.4 pJ. The proposed multiplier can be applied in image processing. The work is designed in Verilog HDL and simulated in Modelsim, Synthesized in Vivado.&lt;/p&gt;

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

In the field of integrated circuits, the computational cost has always been a crucial design metric. In recent years, with the continuous development in the field of computing, the requirements for computation have been growing rapidly. Reducing the computational cost and improving computational efficiency have become the key issues in the field. There are many error-tolerant applications in the multimedia field where approximate computing techniques can be applied to improve computational efficiency and reduce computational costs at the cost of acceptable computational errors. This paper proposed a piecewise linear Mitchell algorithm based on Mitchell logarithmic approximation multiplication algorithm. Additionally, the Pwl-Mit multiplier is designed according to the improved algorithm combined with the data truncation technique. The proposed approximate multiplier has better statistical performance compared with the state-of-the-art multipliers. The design is simulated and synthesized at the TSMC 65 nm process, and its reliability is verified using discrete cosine transform (DCT) transform.

Approximate Multipliers Design Using Approximate Adders for Image Processing Applications

Addition and multiplication are some of the most broadly adopted arithmetic operations in a wide range of applications. This paper proposes new structures of approximate multipliers to optimize the area, delay, and power without affecting the accuracy metrics. Multipliers and adders play a significant role in the functioning of any digital circuit or system. The overall performance of a processor highly depends on the speed of adders and the energy consumption. In this paper, two types of compact error-tolerant approximate adders are designed and used along with approximate 4:2 compressors to improvise the efficiency of the approximate multipliers. The proposed approximate multipliers show good results when compared to the existing structures in terms of area, delay, power, and accuracy. The approximate multipliers are applied to image sharpening and image multiplication applications. The error-tolerant adder’s performance is evaluated in the practical domain using the image blending application. Peak signal-to-noise ratio (PSNR) performance and the structural similarity index metric (SSIM) are used to assess the modeled designs. The proposed approximate multipliers and adders exhibit better performance in terms of PSNR and SSIM and are found to be an optimized design to apply effectively in various error-tolerant image processing applications.

Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements

Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> contiguous bits (a segment of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> bits) is extracted from each of the two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> -bits operand, the two segments are in input to a small <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times m$ </tex-math></inline-formula> internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications.

Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module

This letter proposes an unsigned approximate multiplier architecture segmented into three portions: the least significant portion that contributes least to the partial product (PP) is replaced with a new constant compensation term to improve hardware savings without sacrificing accuracy. The PPs in the middle portion are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple yet efficient error correction module. The most significant portion of the multiplier is implemented using exact logic as approximating it will results in a large error. Experimental results of 8-bit multiplier show that the power and power-delay products are reduced up to 47.7% and 55.2%, respectively, in comparison with the exact design and 36.9% and 39.5%, respectively, in comparison with the existing designs without significant compromise on accuracy.

AppAxO : Designing App lication-specific A ppro x imate O perators for FPGA-based Embedded Systems

Approximate arithmetic operators, such as adders and multipliers, are increasingly used to satisfy the energy and performance requirements of resource-constrained embedded systems. However, most of the available approximate operators have an application-agnostic design methodology, and the efficacy of these operators can only be evaluated by employing them in the applications. Furthermore, the various available libraries of approximate operators do not share any standard approximation-induction policy to design new operators according to an application’s accuracy and performance constraints. These limitations also hinder the utilization of machine learning models to explore and determine approximate operators according to an application’s requirements. In this work, we present a generic design methodology for implementing FPGA-based application-specific approximate arithmetic operators. Our proposed technique utilizes lookup tables and carry-chains of FPGAs to implement approximate operators according to the input configurations. For instance, for an \( \text{M}\times \text{N} \) accurate multiplier utilizing K lookup tables, our methodology utilizes K -bit configurations to design \( 2^K \) approximate multipliers. We then utilize various machine learning models to evaluate and select configurations satisfying application accuracy and performance constraints. We have evaluated our proposed methodology for three benchmark applications, i.e., biomedical signal processing, image processing, and ANNs. We report more non-dominated approximate multipliers with better hypervolume contribution than state-of-the-art designs for these benchmark applications with the proposed design methodology.

Performance analysis and implementation of approximate multipliers on spartan 6 FPGA

Multiplication is a frequently utilized mathematical operation in numerous applications, including signal processing, image processing, and multimedia applications, where multipliers are key components. The speed and large area typically limit their performance. Approximate computing has been critical. These programs are unable to take precise values in specific methods. In them, they like approximate values. Approximate computing methods are used to solve this problem. Approximate multipliers and compressors are constructed by utilizing approximate computation approaches. Because more complicated circuitry is used in many applications, such as DSP, these approximate multipliers and approximate compressors are useful. The suggested work is simulated with Verilog and synthesized with Xilinx ISE 14.6 before being implemented in Spartan – 6. The hardware, size, and speed performance of the suggested multipliers. Both signed and unsigned multipliers are subjected to the multipliers.