Abstract
Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> contiguous bits (a segment of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> bits) is extracted from each of the two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> -bits operand, the two segments are in input to a small <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times m$ </tex-math></inline-formula> internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications.
Highlights
Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay
In this paper we perform a detailed analysis of Static Segmented Multiplier (SSM) and we propose some improvements to the basic architecture
Several approximate multipliers proposed in literature are unsigned only, and operation with signed operands is obtained in three steps: i) operands conversion to sign-modulus representation, ii) modulus multiplication using an inner unsigned multiplier, iii) conversion back of the result in 2s complements
Summary
HE request of energy-efficient and high-performance computing systems is steadily increasing, given the explosion of ubiquitous computing devices and the amount of data to be processed. In a Static Segmented Multiplier (SSM) [46] the operands are statically split into two m-bit segments This approach greatly simplifies hardware implementation, reducing power consumption, since leading-one detectors and shifters are not required. To the best of our knowledge, no signed static segmented multipliers have been investigated so far, while the only paper to date that tries to improve the accuracy of static segmented multipliers is [48] that, requires the introduction of two carry-propagate adders before the m × m inner multiplier, with significant increase of delay and power. We have synthesized the circuits developed in this paper and several previously proposed approximate multipliers, using a commercial 28nm library, for 8bit operands. Syntheses show that our circuits, compared to previously prosed approximate multipliers, provide very good error-electrical performance trade-off.
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