Design and Analysis of Approximate 4-2 Compressor for Efficient Multiplication

Abstract

Approximation computing concepts have been introduced and studied to provide sufficient accuracy with low power. Many approximate 4-2 compressor designs and methods are proposed to build approximate multipliers. However, most of the designs used for conventional approximate multipliers have been proposed to achieve low power by compromising accuracy or to maintain accuracy with low performance. In this study, a new 4-2 compressor is proposed to improve the error rate, delay, and power consumption. The proposed compressor was used to build an approximate multiplier. Transistor-level SPICE simulations with a high-performance 32-nm predictive technology model (PTM) were conducted to verify the efficiency of the proposed design. The results show that the proposed 4-2 compressor design can achieve up to 4.2% and 22.5% improvement in power consumption and delay, respectively. The proposed multiplier design can achieve up to 4.2% and 15.5% improvement in power consumption and error metrics, respectively. Compared to other designs, the proposed multiplier has lower error in small operand operations.