Approximate Multipliers Design Using Approximate Adders for Image Processing Applications

Abstract

Addition and multiplication are some of the most broadly adopted arithmetic operations in a wide range of applications. This paper proposes new structures of approximate multipliers to optimize the area, delay, and power without affecting the accuracy metrics. Multipliers and adders play a significant role in the functioning of any digital circuit or system. The overall performance of a processor highly depends on the speed of adders and the energy consumption. In this paper, two types of compact error-tolerant approximate adders are designed and used along with approximate 4:2 compressors to improvise the efficiency of the approximate multipliers. The proposed approximate multipliers show good results when compared to the existing structures in terms of area, delay, power, and accuracy. The approximate multipliers are applied to image sharpening and image multiplication applications. The error-tolerant adder’s performance is evaluated in the practical domain using the image blending application. Peak signal-to-noise ratio (PSNR) performance and the structural similarity index metric (SSIM) are used to assess the modeled designs. The proposed approximate multipliers and adders exhibit better performance in terms of PSNR and SSIM and are found to be an optimized design to apply effectively in various error-tolerant image processing applications.