The Hardware Cost and Computing Accuracy Trade-off in Multipliers using Imprecise 4-2 Compressors for Image Processing Applications

Abstract

Approximate computing has been widely used in image processing applications to significantly reduce the hardware cost of circuits; however, this induces a sacrifice in computing accuracy. The compromise between accuracy and hardware cost in approximate multipliers has not been investigated yet. To address this issue, this paper proposes a set of approximate 8×8 Dadda multipliers built by using an efficient imprecise 4-2 compressor. The compressor introduces symmetrical errors into the truth table of the exact design to reach a simpler structure. Furthermore, as an important image processing application, image multiplication is implemented with the proposed multipliers. Synthesis and simulation results show that the overall performance of the multipliers varies depending on the various assessment criteria. Utilization of the modified compressor in the multipliers results in area, delay, and power reductions of 38%-72%, 14%-33%, and 39%-77%, respectively, compared to the exact design, while maintaining acceptable computing accuracy in image multiplication. According to the results, the proposed multipliers achieve a better trade-off between energy efficacy and computing accuracy than the existing designs, which could be certified as options for exact multipliers in image processing.