Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application

Abstract

Approximate computing finds its application in image processing, machine learning, data mining and multimedia data processing. The paper proposes a scalable and lightweight <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> approximate multiplier, which is designed to efficiently utilize the FPGA resources. We have divided the partial product matrix and selectively chosen the input variables for the effective usage of the LUTs and carry-chain. The bit error position due to the approximation is reduced by assigning the possible lower bits to ‘1’ which reduces the maximum error magnitude from 16 to 4. The proposed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> approximate multiplier achieves a reduction in area, power and latency of 26.7%, 57.6% and 60.1% respectively compared to the Xilinx multiplier IP. The proposed multiplier is used as a building block to implement <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> approximate multipliers for image sharpening applications. We achieve a high PSNR value of 69.4 dB using the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> approximate multiplier.