Approximate Multipliers Research Articles

Design of Imprecise Multipliers by Using Approximate Technique for Error Resilient Applications

Approximate computing is the perfect way for error resilient applications with progress in speed and power but tradeoff with computational accuracy. In this paper, Imprecise Multipliers (IMs) are realized by segregating the partial products into two segments. The most significant bit (MSB) segment is accumulated as per Dadda tree structure and the least significant bit (LSB) segment is accumulated by approximate technique. The proposed Imprecise Multipliers, namely [Formula: see text] and [Formula: see text] are realized using Verilog HDL and simulated using TSMC 65[Formula: see text]nm process. For sake of comparison, the proposed multipliers [Formula: see text] and [Formula: see text] are compared with existing approximate multipliers. From the reported results, it may be noted that [Formula: see text] performs better in terms of area–delay product, power–delay product. While [Formula: see text] achieves a higher peak signal-to-noise ratio (PSNR) among all the multipliers existing in the literature.

Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators

Libraries of approximate circuits are composed of fully characterized digital circuits that can be used as building blocks of energy-efficient implementations of hardware accelerators. They can be employed not only to speed up the accelerator development but also to analyze how an accelerator responds to introducing various approximate operations. In this paper, we present a methodology that automatically builds comprehensive libraries of approximate circuits with desired properties. Target approximate circuits are generated using Cartesian genetic programming. In addition to extending the EvoApprox8b library that contains common approximate arithmetic circuits, we show how to generate more specific approximate circuits; in particular, MxN-bit approximate multipliers that exhibit promising results when deployed in convolutional neural networks. By means of the evolved approximate multipliers, we perform a detailed error resilience analysis of five different ResNet networks. We identify the convolutional layers that are good candidates for adopting the approximate multipliers and suggest particular approximate multipliers whose application can lead to the best trade-offs between the classification accuracy and energy requirements. Experiments are reported for CIFAR-10 and CIFAR-100 data sets.

Design of a High Speed Approximate Multiplier with Inexact Compressor Adder

Design of a High Speed Approximate Multiplier with Inexact Compressor Adder

Architecture and Performance Analysis of Approximate Multipliers for DSP Application

Architecture and Performance Analysis of Approximate Multipliers for DSP Application

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

Approximate multipliers attract a large interest in the scientific literature that proposes several circuits built with approximate 4-2 compressors. Due to the large number of proposed solutions, the designer who wishes to use an approximate 4-2 compressor is faced with the problem of selecting the right topology. In this paper, we present a comprehensive survey and comparison of approximate 4-2 compressors previously proposed in literature. We present also a novel approximate compressor, so that a total of twelve different approximate 4-2 compressors are analyzed. The investigated circuits are employed to design $8\times 8$ and $16\times 16$ multipliers, implemented in 28nm CMOS technology. For each operand size we analyze two multiplier configurations, with different levels of approximations, both signed and unsigned. Our study highlights that there is no unique winning approximate compressor topology since the best solution depends on the required precision, on the signedness of the multiplier and on the considered error metric.

Significance-Driven Logic Compression for Energy Efficient Multiplier Design

Approximate Arithmetic is a new design paradigm that is being used in many applications which are tolerant to imprecision and do not require accurate results. It can reduce circuit complexity, delay and energy consumption by relaxing accuracy requirements. The partial product bit matrix can be reduced based on their progressive bit significance using a Significance Driven Logic Compression(SDLC) approach. Further, the complexity of the approximate multiplier can be reduced by using Approximate adders in place of exact adders in the accumulation method. Removing some of the transistors from an accurate adder will result in an approximate adder. By using approximate adders which have less number of transistors, the power, propagation delay, and the switching capacitance can be reduced. In this paper, approximate multipliers are implemented using different approximate adders and they are compared with an exact multiplier in terms of power, delay and energy savings.

Error-aware Design Procedure to Implement Energy-efficient Approximate Squaring Hardware

Background:: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. Objective:: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring. Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving. Conclusion:: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers

Approximate recursive multipliers exhibit low-power operation because they are designed using smaller power-efficient approximate multiplier blocks. These building blocks can be configured by varying the approximation levels for a wide range of larger multiplier sizes. However, most of the building blocks proposed for recursive multipliers are either slightly inaccurate or hardware-efficient with limited accuracy. In this brief, hybrid partial product-based building blocks are proposed by considering the probability distribution of the input operands. An efficient hardware implementation of approximate 4×4 multipliers is achieved, while maintaining the required accuracy. Moreover, high-performance approximate NOR-based half adder (NxHA) and full adder (NxFA) cells are proposed for use in a 4×4 multiplier. Three different strategies (Ax8-1/2/3) are further proposed and analyzed for utilizing the 4×4 multipliers when designing larger multipliers. Ax8-2 provides the best trade-off among the designs with a moderate MRED. A reduction of 30 and 17 percent in the MRED is achieved compared to previous best energy-optimized and MRED-optimized designs. Among the designs with higher MREDs, Ax8-3 exhibits the smallest MRED and PDP. Moreover, it shows an improvement of 7 to 28 percent in delay compared to existing approximate recursive designs. As a case study, image multiplication is evaluated; a high peak signal-to-noise ratio (PSNR) with a value close to 50dB is obtained for the proposed multiplier designs.

LPQ-SAM: A Low-Power Quality Scalable Approximate Multiplier

Approximate computing allows compromising accuracy to attain energy and performance efficient designs. However, the accuracy requirements of many applications change on runtime and it has been often observed that traditional approximate hardware tends to either provide unacceptable results or leads to an unnecessary computational effort. Quality scalable configurations can overcome these limitations. With the same motivation, we propose a low-power quality scalable approximate multiplier (LPQ-SAM) in this paper. This low power multiplier has various accuracy reconfigurable modes, including an accurate one and thus, it can be used for both error-resilient and exact applications. LPQ-SAM is exhaustively tested for different error metrics and it has been observed that in the approximate mode, it provides up to 19% and 55% power reduction compared to the exact Booth and Wallace multipliers, respectively. For illustration purposes, we demonstrated the effectiveness of LPQ-SAM on a real-time application, i.e., image masking.

Power Efficient and High-Accuracy Approximate Multiplier with Error Correction

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

Design of Ultra-Low Power Consumption Approximate 4–2 Compressors Based on the Compensation Characteristic

Approximate computing is tentatively applied in some digital signal processing applications which have an inherent tolerance for erroneous computing results. The approximate arithmetic blocks are utilized in them to improve the electrical performance of these circuits. Multiplier is one of the fundamental units in computer arithmetic blocks. Moreover, the 4-2 compressors are widely employed in the parallel multipliers to accelerate the compression process of partial products. In this brief, three novel approximate 4-2 compressors are proposed and utilized in 8-bit multipliers. Meanwhile, an error-correcting module (ECM) is presented to promote the error performance of approximate multiplier with the proposed 4-2 compressors. In this brief, the number of the approximate 4-2 compressor's outputs is innovatively reduced to one, which brings further improvements in the energy-efficiency. Compared with the exact 4-2 compressors, the simulation results indicate that the proposed approximate compressors UCAC1, UCAC2, UCAC3 achieve 24.76%, 51.43%, and 66.67% reduction in delay, 71.76%, 83.06%, and 93.28% reduction in power and 54.02%, 79.32%, and 93.10% reduction in area, respectively. And the utilization of these proposed compressors in 8-bit multipliers brings 49.29% reduction of power consumption on average.

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning

Approximate computing provides an emerging approach to design high performance and low power arithmetic circuits. The logarithmic multiplier (LM) converts multiplication into addition and has inherent approximate characteristics. In this article, dynamic range approximate LMs (DR-ALMs) for machine learning applications are proposed; they use Mitchell’s approximation and a dynamic range operand truncation scheme. The worst case (absolute and relative) errors for the proposed DR-ALMs are analyzed. The accuracy and the hardware overhead of these designs are provided to select the best approximate scheme according to different metrics. The proposed DR-ALMs are compared with the conventional LM with exact operands and previous approximate multipliers; the results show that the power-delay product (PDP) of the best proposed DR-ALM (DR-ALM-6) are decreased by up to 54.07 percent with the mean relative error distance (MRED) decreasing by 21.30 percent compared with 16-bit conventional design. Case studies for three machine learning applications show the viability of the proposed DR-ALMs. Compared with the exact multiplier and its conventional counterpart, the back-propagation classifier with DR-ALMs with a truncation length larger than 4 has a similar classification result for the three datasets; the K-means clustering application with all DR-ALMs has a similar clustering result for four datasets; and the handwritten digit recognition application with DR-ALM-5 or DR-ALM-6 for LeNet-5 achieves similar or even slightly higher recognition rate.

An efficient design of low-power and high-speed approximate compressor in FinFET technology

Nowadays, computer arithmetic logic units extensively utilize inexact computing to improve performance in nano-electronics. One of the vital computational components in microprocessors and digital signal processors is multiplier. Approximate 4:2 compressor is a key element in an approximate multiplier and the optimal design of the compressor directly guarantees the performance of the multiplier. This paper proposes a new low-power and high-speed approximate 4:2 compressor design which leads to a high-speed multiplier. We have designed an 8-bit Dadda multiplier composed of our new compressor and analyzed the multiplier in terms of the error metrics in comparison with its counterparts. As an image processing application of our multiplier, we compared the quality metrics of the image multiplication for different under-test multipliers obtained from the previous studies considering several benchmark images. The simulations are carried out by HSPICE in 14 nm FinFET Technology and approve the efficiency of our design.

Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation

In approximate operators, dynamic truncation allows trading off energy and quality of computation at runtime. Although it exploits the specificity of the data being processed, its significant energy overhead over simple static truncation fundamentally limits its energy benefits. This brief describes a simple and efficient design methodology that reduces the energy consumption of dynamically truncated multipliers, based on a smart mapping of the partial products. A configurable hardware correction strategy is also proposed to enable graceful quality degradation, as well as more aggressive energy reduction at a given quality. When applied to Wallace multipliers, the proposed approach achieves quality, in terms of Mean Error Distance, up to 11× higher than the conventional dynamic truncation, at the same energy. In the case study of Discrete Cosine Transform compression, the proposed approximate multiplier reaches image qualities by 15-35% better, compared to prior art.

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

EANN: Energy Adaptive Neural Networks

This paper proposes an Energy Adaptive Feedforward Neural Network (EANN). It uses multiple approximation techniques in the hardware implementation of the neuron unit. The used techniques are precision scaling, approximate multiplier, computation skipping, neuron skipping, activation function approximation and truncated accumulation. The proposed EANN system applies the partial dynamic reconfiguration (PDR) feature supported by the FPGA platform to reconfigure the hardware elements of the neural network based on the energy budget. The PDR technique enables the EANN system to remain functioning when the available energy budget is reduced by factors of 46.2% to 79.8% of the total energy of the unapproximated neural network. Unlike the conventional operation that only uses certain amount of energy and cannot function properly if the energy budget falls below that energy level, the EANN system remains functioning for longer time after energy drop at the expense of less accuracy. The proposed EANN system is highly recommended in limited-energy applications as it adapts the hardware units to the degraded energy at the expense of some accuracy loss.

AxCEM: Designing Approximate Comparator-Enabled Multipliers

Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often suggests employing approximate computing to improve the energy-efficiency, performance, and area of floating-point multipliers. Prior work has shown that employing hardware-oriented approximation for computing the mantissa product may result in significant system energy reduction at the cost of an acceptable computational error. This article examines the design of an approximate comparator used for preforming mantissa products in the floating-point multipliers. First, we illustrate the use of exact comparators for enhancing power, area, and delay of floating-point multipliers. Then, we explore the design space of approximate comparators for designing efficient approximate comparator-enabled multipliers (AxCEM). Our simulation results indicate that the proposed architecture can achieve a 66% reduction in power dissipation, another 66% reduction in die-area, and a 71% decrease in delay. As compared with the state-of-the-art approximate floating-point multipliers, the accuracy loss in DNN applications due to the proposed AxCEM is less than 0.06%.

SyRG-PV-BES-Based Standalone Microgrid Using Approximate Multipliers Based Adaptive Control Algorithm

This article deals with the adaptive control algorithm to maximize the distributed generations (DGs) in islanded microgrid. The approximate multiplier least mean square (AMLMS) control scheme is used for the extraction of fundamental load component with reduced steady state error and faster convergence to provide better performance than conventional LMS control. This control focuses on reduction of complexity of LMS by adding multipliers in the finite impulse response filter and updating the coefficients. The AMLMS control algorithm for a voltage source converter is also effective in compensating harmonics for power quality improvement of islanded microgrid system while feeding nonlinear load. In an islanded microgrid at ac side, a synchronous reluctance generator based pico-hydropower generator is used because it is economical than other conventional generators. At dc side, a photovoltaic array and a bidirectional dc–dc converter (BDC) are used. The BDC with a storage battery maintains the optimal power flow to provide the power equilibrium between load and sources through dc-link voltage regulation. The BDC also mitigates the second order harmonic from the battery charging and discharging current. Test and simulation results validate the effectiveness of AMLMS control under steady and dynamic conditions of solar insolation change and load unbalance.

Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier

Many applications, such as machine learning and sensor data analysis, are statistical in nature and can tolerate some level of inaccuracy in their computation. Approximate computing is a viable method to save energy and increase performance by controllably trading off energy for accuracy. In this paper, we propose a tiered approximate floating point multiplier, called CFPU, which significantly reduces energy consumption and improves the performance of multiplication at a slight cost in accuracy. The floating point multiplication is approximated by replacing the costly mantissa multiplication step of the operation with lower energy alternatives. We process the data by using one of the three modes: a basic approximate mode, an intermediate approximate mode, or on the exact hardware, depending on the accuracy requirements. We evaluate the efficiency of the proposed CFPU on a wide range of applications including twelve general OpenCL ones and three machine learning applications. Our results show that using the first CFPU approximation mode results in $3.5\times $ energy-delay product (EDP) improvement, compared to a GPU using traditional floating point units (FPUs), while ensuring less than 10% average relative error. Adding the second mode further increases the EDP improvement to $4.1\times $ , compared to an unmodified FPU, for less than 10% error. In addition, our results show that the proposed CFPU can achieve $2.8\times $ EDP improvement for multiply operations as compared to state-of-the-art approximate multipliers.

Delay and area efficient approximate multiplier using reverse carry propagate full adder

The performance and power of error resilient applications will rise with a decrease in designing complexness due to approximate computing. This paper includes the new method for the approximation of multipliers. Variable likelihood terms are produced by the alteration of partial products of the multiplier. Based on the probability statistics, the accumulation of altered partial products leads to the variation of logic complexity. Here the estimate is implemented in 2 variables of 16-bit multiplier and in the final stage with reverse carry propagate adder(RCPA). The reverse carry propagate adder have carry signal propagation from the most significant bit(MSB) to the least significant bit(LSB), which results in greater relevance to the input carry than the output carry. The technique of carry circulation in reverse order with delay variations increases the stability. Utilizing the RCPA in approximate multiplier provide 21% and 7% improvements in area and delay. On comparing, this structure is resilient to delay variations than the ideal approximate adder.