Approximate Multipliers Research Articles

Improving the accuracy of approximate multipliers based on the characteristics of 4:2 compressors

Approximate computing is a new trend applied in many applications such as multimedia processing and pattern recognition, which can tolerate a certain amount of error since they are inherently error-tolerant. In this paper, we use two different methods to modify and improve the accuracy of the previous approximate multipliers. In the first method, we use an error recovery module in the structure of the existing approximate multipliers based on the characteristics of their approximate compressors. In the second method, by considering the accuracy parameters of the previous designs, we combine the previous compressors to improve the efficiency of the existing approximate multipliers. The proposed circuits are simulated using HSPICE with the 7 nm FinFET model. The efficacy of the multipliers in real-life applications such as image processing and neural networks are evaluated using MATLAB. The results show that using the first method increases the accuracy parameters of the previous designs, while it does not lead to considerable power and delay overheads. However, utilizing the second method can improve both the accuracy and hardware characteristics of the previous designs. For example, the PM2 multiplier, using the first proposed method, improves the MED and MRED, as two widely used accuracy metrics, by 36.7% and 21.6%, whereas using this method slightly increases the power-delay product (PDP) by 2.7%. In addition, the PM6 multiplier equipped with the second proposed method improves the MED and MRED values by 26% and 17% and has a 5.2% lower PDP.

Design of approximate Booth multipliers based on error compensation

With the rapid development of the Internet of Things, terminal equipment is greatly restricted in hardware resources and power supply. Therefore, there is an urgent need for new low-power computing units. Aiming at the problem of high power consumption of the arithmetic unit, a low-power approximate Booth multiplier based on complementary error is proposed. Among them, the new Booth encoder will produce positive errors and the approximate Wallace tree structure will produce negative errors. The mutual compensation of the two errors can improve the accuracy of the approximate Booth multiplier to a certain extent. The experimental results show that, compared with the existing multipliers, the proposed approximate Booth multiplier reduces the power consumption by 20.62% and the delay by 14.45%, saving 19.68% of the area. At the same time, its normalized average error distance is better than the existing approximate multiplier. Finally, the results of image filtering verify the practicality of the proposed approximate Booth multiplier.

A New Approximate (8; 2) Compressor for Image Processing Applications

Approximate computing is one of the methods to improve performance in various error-resilient applications such as image and video processing. Multipliers are part of their computing unit that often requires many resources. In this paper, an approximate (8; 2) compressor is designed and compared with other available approximate compressors for quality, power consumption, delay and area in the circuit. The proposed approximate compressor is used in and multipliers. To show the quality of the proposed compressor, the proposed approximate multiplier of used to multiply two images in MATLAB tools, then qualitative parameters of SSIM and PSNR were measured and acceptable results were obtained. Also, the MED and NED accuracy parameters indicate the acceptable error rate in the output of the proposed multiplier circuit. Finally, we synthesized the proposed approximate compressor and multiplier designs by a Synopsys Design Compiler. The proposed multiplier can improve delay, area and Power Delay Products by 5%, 17%, and 8%, respectively, compared to other similar existing approximate multipliers.

An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient Applications

Approximate computing is a promising paradigm for trading off accuracy to improve hardware efficiency in error-resilient applications such as neural networks and image processing. This brief presents an ultra-efficient approximate multiplier with error compensation capability. The proposed multiplier considers the least significant half of the product a constant compensation term. The other half is calculated precisely to provide an ultra-efficient hardware-accuracy trade-off. Furthermore, a low-complexity but effective error compensation module (ECM) is presented, significantly improving accuracy. The proposed multiplier is simulated using HSPICE with 7nm tri-gate FinFET technology. The proposed design significantly improves the energy-delay product, on average, by 77% and 54% compared to the exact and existing approximate designs. Moreover, the proposed multiplier’s accuracy and effectiveness in neural networks and image multiplication are evaluated using MATLAB simulations. The results indicate that the proposed multiplier offers high accuracy comparable to the exact multiplier in NNs and provides an average PSNR of more than 51dB in image multiplication. Accordingly, it can be an effective alternative for exact multipliers in practical error-resilient applications.

Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

SummaryRecustomize finite impulse response (RFIR) filter is designed to achieve lesser power consume, cost, area, and higher speed of system operation. This is used to remove the noises from the image and signal. Previously, several filters were designed for removing noises, but that filters consume more area, power, cost, and delay and did not provide accurate results and the error rate was increased. To overcome these issues, this work is proposed. In this work, the Recustomize finite impulse response (RFIR) filter is designed using truncation‐based scalable rounding approximate multiplier (TOSAM) and error reduced carry prediction approximate adder (ERCPAA) for image processing application. Here, TOSAM‐ERCPAA is used to speed up the filter design with less area and less power consumption. The proposed ERCPAA adder is divided into three blocks, such as carry prediction logic, approximate full adder cells array, constant truncation along error lessening logic, which can reduce the power and area. The proposed RFIR‐ TOSAM‐ERCPAA filter is designed and executed in Verilog programming language and the simulation is done in Xilinx ISE 14.5 design tools.

Efficient approximate multipliers with adjustable accuracy

ABSTRACT The number of smart devices grows rapidly, and the main leakage of many of these devices is their limited batteries, in addition to the need for a fast and low-power computing system. Approximate calculations are an excellent method for such systems to achieve higher speed and less area and power consumption at the cost of lower accuracy. Furthermore, in many applications with inherent tolerance for insignificant inaccuracies such as image processing, approximate computing can be used to achieve acceptable performance with higher speed, lower power or area consumption. In this work, approximate multiplier structures are proposed based on working on the partial product trees with the aim of reducing area consumption and increasing accuracy. Comprehensive experimental analysis is performed to evaluate the performance of the proposed multiplier in terms of area, delay, power consumption, and accuracy. The results show that our suggested design improves at most 29% of power consumption, 11% of delay, and 55% of the area rather than an exact multiplier. Moreover, the performance of our multipliers is investigated based on the peak signal noise ratio (PSNR) for processing two images, which lead to 56.65 and 23.6 dB.

Exact and approximate multiplications for signal processing applications

Approximate computing is an emerging technique that can be used for developing power, area and delay efficient circuits at the cost of loss of accuracy. This paper investigates the possibility of efficient exact multipliers through the use of improved compressors and counters and thereafter deriving approximate multiplier structures to achieve a higher percentage of logic optimization at the expense of the lowest possible error. NAND gate based array structure with reduced complexity is used for generating the partial products for both the exact and approximate multipliers. Two variants of the efficient exact multiplier are proposed. The proposed exact multiplier EM-1 is area and power efficient, whereas EM-2 is delay and energy efficient. Two variants of 4:2 compressors are introduced for developing approximate multipliers. The proposed multipliers excel most of the state-of-the-art existing multipliers in terms of the important performance metrics. The proposed exact and approximate multiplier designs are employed for developing ECG denoising FIR filter for the elimination of power line interference and the corresponding performance improvement is illustrated. Cadence RTL compiler v11.10 with GPDK 45 nm standard cell library is used for the synthesis. The simulation of all the multipliers is done by running a test bench program using modelsim.

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

SummaryA design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation based scalable rounding approximate multiplier (APM‐CDF‐ESDCSA‐TOSAM) is proposed in this article for image processing application. The proposed ESDCSA‐TOSAM is used to speed up the filter design with less area and less power consumption. In the existing designs, a carry select adder was used that was a rapid binary adders, even though, it consumes maximal area and power. For that reason, lower power, area efficient with higher speed eminent speed dual carry select adder (ESDCSA) is used in this work. The proposed ESDCSA is a fastest binary adder, which consumes less power and area. To design the ESDCSA, three blocks are used: half sum with carry generator (HSCG), final carry generator (FCG), final sum generator (FSG), these are reducing the power and area. TOSAM is used to reduce more partial products by truncating each input operands depending on its leading one‐bit position. The proposed filter is designed on Xilinx ISE 14.5 design tools. The experimental performance of the proposed filter attains lower delay 59.61%, 37.91%, 34.99%, 28.09%, 44.04% and 38.23% compared with existing filters.

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy. To overcome these issues, the digital circuits are applied to the Deep Learning (DL) approaches for higher accuracy. In recent times, DL is the method that is used for higher learning and prediction accuracy in several fields. Therefore, the Long Short-Term Memory (LSTM) is a popular time series DL method is used in this work for approximate computing. To provide an optimal solution, the LSTM is combined with a meta-heuristics Jellyfish search optimisation technique to design an input aware deep learning-based approximate multiplier (DLAM). In this work, the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier. The optimal hyperparameters of the LSTM model are identified by jelly search optimisation. This fine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy. The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a function of area, delay, power and error metrics. The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approximate computing multiplier achieved a superior area and power reduction with very good results on error rates.

Approximate Multiplier based on Low power and reduced latency with Modified LSB design

The devised approximation multiplier can adapt the precision and processing power needed formul triplication sat run-time based on the needs of the user. To decrease error distance, we also suggest a straight forward error compensation circuit. There are two types of approximate multi pliers. Dynamic voltages caling can be used for the first kind, which controls the timing route of the multiplier. If the voltage is lower, the critical path will take longer to complete. As a result, when the time path is violated, errors occurs and approximated results are produced. These cond types involves redesigning precise multiplier circuits like the Wallace Tree Multiplier and Dadda Tree Multiplier in order to change the functional behaviors of multipliers. Most of the earlier research on rebuilding multipliers suggested erroneous m-n compressors, which have m inputs and producen outputs. It dynamically reduces the area covered under the multiplier LSB which enables the MSB in accurate manner and LSB in approximate manner. This convolution al system approach is regarded to sequential cover up more than 32 bit multiplier. Since the accompanied circuit reduce then tire area by10times lesser than original multiplier, this conventional unit is regarded as abled circuit in the segment. Since the process of compressing partial products absorbed the majority of the multiplier energy and resulted in a consider able route delay, these incorrect compressors were utilized to compress the partial products within multiplication. These functionality are over come through our experimental setup.

A Review and Analysis on Decoder Based Approximate Multiplier (DeBAM)

A Review and Analysis on Decoder Based Approximate Multiplier (DeBAM)

DESIGN AND IMPLEMENTATION OF A NOVEL ENERGY-EFFICIENT MULTIPLIER CIRCUIT USING APPROXIMATE COMPUTING TECHNIQUE

A promising paradigm for many imprecision-tolerant applications has recently been identified as approximate arithmetic. By reducing accuracy standards, it can significantly reduce circuit complexity, latency, and energy consumption. In this research, we present a unique significance-driven logic compression (SDLC) approach for an energy-efficient approximate multiplier design. An algorithmic and adjustable lossy compression of the partial product rows based on their progressive bit importance is the core of this approach. To lessen the number of product rows, the resulting product terms are then commutatively remapped. As a result, the multiplier's complexity in terms of the number of logic cells and the lengths of critical routes is significantly decreased.

An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

Design Optimization of a 4-2 Compressor for Low-cost Approximate Multipliers

Approximate computing can enhance hardware efficiency for error-tolerant applications. This technique can be applied to basic arithmetic operations such as multiplication. Approximate multiplication is generally implemented using several approximate compressors. In this paper, we propose an optimized 4-2 approximate compressor based on an existing compressor. We elaborate Boolean expressions for the compressor to replace the original gates with compound gates that reduce the hardware resource consumption. Compared to the original design, the optimized compressor

Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, an open-source adaptable approximate multiplier design driven by input distribution and polarity is proposed to generate optimized approximate multipliers to trade off between the application-level performance and the hardware cost. The proposed method minimizes the average square of the absolute error of an approximate multiplier according to the probability distributions of operands extracted from the target application with consideration of input polarity, achieving low hardware cost and negligible application-level performance loss. The proposed method can generate unsigned multipliers (or signed multipliers) based on the Braun multiplier (or Baugh–Wooley multiplier). To demonstrate the effectiveness of the method, three different-scale quantized DNNs, including LeNet, AlexNet, and VGG16 with 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 8 unsigned multiplication and an adaptive least mean square (LMS)-based finite impulse response (FIR) filter with 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 16 fixed-point signed multiplication, are evaluated. In the DNN training process, a noise training technique is adopted to reduce the accuracy loss due to the approximation. When compared to the state-of-the-art approximate multipliers, the generated multipliers can achieve up to 26.4% and 27.1% product of power, delay, and area gains with negligible application-level performance loss in VGG16 and FIR applications, respectively.

Design and Analysis of Multipliers for DNN application using approximate 4:2 Compressors

The demand for Deep Learning applications in resource constrained devices is booming in recent years. Theuse of Deep Neural Network (DNN) is the leading method in these applications which has error resilient nature.This allows the use of Approximate Computing for efficient computation to leverage efficiency accuracy tradeoff by replacing Approximate Multiplier in place of exact multipliers. In this paper we proposed ApproximateCompressors and compared them in different cases of 8 bit integer dadda multipliers in terms of the Error metricsand accuracy in real life object classification applications. The approximate multipliers are designed using differentcompressors and used to perform multiplication in ResNet. We have proposed two approximate compressorsdesigns Design 1 and Design 2.The proposed 4:2 compressors design shows the more correct outputs and lessWorst Case Relative Error (WCRE) in the range of 2-16. Our proposed 4:2 compressor Design1 is utilized in themodified Reduction circuitry of dadda multiplier and shows the accuracy of 81.6 % for DNN application

Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations

The performance of nanoscale semiconductor technologies has become susceptible to high temperatures and aging phenomena. While guard-bands have conventionally been used to combat degradation-induced timing violations, approximations have recently been leveraged to compensate for degradations in lieu of adding timing guard-bands, without a loss in performance. However, only simple approximation techniques such as truncation have been considered in prior work. In this paper, a wide range of approximate arithmetic circuits including adders and multipliers using various sophisticated approximation techniques are investigated to cope with aging- and temperature-induced degradations. To this end, approximate circuits are first characterized for their delay increase under degradations. With this, we then determine the approximation level required to compensate for guard-bands under different degradations. Degradation-aware logic synthesis results show that the simple use of truncated arithmetic circuits leads to a higher quality loss compared to using other approximate circuits. However, a truncated multiplier has the lowest error distance towards a reliable operation in 10 years. The approximate multipliers with configurable error recovery are most suitable when the level of degradation is higher, e.g., at a temperature of 70 °C. The characterization of degradation at the circuit level is then used for design exploration at the architecture level without the need for further gate-level simulations. For three different image processing applications, experimental results show that guard-bands can be mitigated while maintaining an output result with a high visual quality.

Compressor based hybrid approximate multiplier architectures with efficient error correction logic

A new approximate unsigned multiplier architecture has been proposed in this paper, which aims to minimize the area utilized and power consumed while maintaining high accuracy. The proposed architecture is segmented into the least significant region (LSR), the approximate region, and the accurate region (most significant region). In LSR, the partial products (PPs) are reduced using four methods. In contrast, in the approximate region, two new approximate compressors are used to reduce the PPs, and the error arising from the approximate compressors is neutralized using an efficacious error-correcting module. For the 8-bit multipliers, the results indicate that the proposed designs, when compared against the exact design, achieve an increment of 26.5% and 32.2% in power and power-delay-product, respectively, and when compared with other approximate designs, achieve an improvement of 18.4% and 26.4%, respectively. Finally, proposed designs are evaluated using image processing and neural network applications.

High-performance, energy-efficient, and memory-efficient FIR filter architecture utilizing 8x8 approximate multipliers for wireless sensor network in the Internet of Things

IoT uses wireless sensor networks (WSN) to deploy many sensors to track environmental and physical parameters. The WSN measurements are frequently contaminated and altered by noise. The noise in the signal increases the sensor node’s computation and energy utilization, resulting in less longevity of the sensor node. The Finite Impulse Response (FIR) filter is commonly employed in WSN to pre-process sensed signals to remove noise from the sensed signals using delay elements, multipliers, and adders. Traditional multiplier-based FIR filter designs result in hardware-intensive multipliers that consume a lot of energy, and area and have low computation speed. These drawbacks make them unsuitable for IoT-based WSN systems with stringent power efficiency necessities. Approximate computing enhances the energy efficiency of an FIR filter. Arithmetic circuits utilizing approximate computing improve the hardware performance, with some loss of accuracy to save energy utilization and boost speed. A novel approximate multiplier architecture employing a fast and straightforward approximation adder is proposed in this study. Approximate multiplier M1 using OR gate and approximate multiplier M2 using proposed approximate adders are compared. The proposed approximate adder is suited for building an adder tree to accumulate partial product (PP) because it is less complicated than traditional adders. Compared to a one-bit-full adder, the critical path delay (CPD) is reduced significantly in the proposed methods. The accuracy comparison of M1. M2 and Wallace tree using the normalized mean error distance (NMED), the mean relative error distance (MRED), the maximum error (ME), and the error rate (ER) with the number of bits utilized for reducing error. For the area (delay) optimized circuit, when the bit used is 4, the delay is 0.4 ns for M1, 0.43 ns for M2, and 1.08 ns for the Wallace tree multiplier. For the delay (area) optimized circuit, when the bit used is 4, the delay is 0.16 ns for M1, 0.16 ns for M2, and 0.40 ns for the Wallace tree multiplier. To more accurately evaluate performance at the circuit level, the PDP and ADP are computed. The NMED, MRED, ME, and ER versus PDP and ADP are computed. The proposed multipliers M1 and M2 are compared with existing approximate multipliers. When an equivalent MRED, NMED, or ER is taken into account, M1 has the smallest ADP and PDP among other multipliers. The very low likelihood of a significant ED occurring is indicated by the small values of NMED and MRED in M1 and M2. The proposed solutions effectively reduce delay, area, and power while maintaining increased accuracy and performance.

Thermal-Aware Design for Approximate DNN Accelerators

Recent breakthroughs in Neural Networks (NNs) have made DNN accelerators ubiquitous and led to an ever-increasing quest on adopting them from Cloud to edge computing. However, state-of-the-art DNN accelerators pack immense computational power in a relatively confined area, inducing significant on-chip power densities that lead to intolerable thermal bottlenecks. Existing state of the art focuses on using approximate multipliers only to trade-off efficiency with inference accuracy. In this work, we present a thermal-aware approximate DNN accelerator design in which we additionally trade-off approximation with temperature effects towards designing DNN accelerators that satisfy tight temperature constraints. Using commercial multi-physics tool flows for heat simulations, we demonstrate how our thermal-aware approximate design reduces the temperature from 139 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula> C, in an accurate circuit, down to 79 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula> C. This enables DNN accelerators to fulfill tight thermal constraints, while still maximizing the performance and reducing the energy by around 75% with a negligible accuracy loss of merely 0.44% on average for a wide range of NN models. Furthermore, using physics-based transistor aging models, we demonstrate how reductions in voltage and temperature obtained by our approximate design considerably improve the circuit’s reliability. Our approximate design exhibits around 40% less aging-induced degradation compared to the baseline design.