Compressor based hybrid approximate multiplier architectures with efficient error correction logic

Abstract

A new approximate unsigned multiplier architecture has been proposed in this paper, which aims to minimize the area utilized and power consumed while maintaining high accuracy. The proposed architecture is segmented into the least significant region (LSR), the approximate region, and the accurate region (most significant region). In LSR, the partial products (PPs) are reduced using four methods. In contrast, in the approximate region, two new approximate compressors are used to reduce the PPs, and the error arising from the approximate compressors is neutralized using an efficacious error-correcting module. For the 8-bit multipliers, the results indicate that the proposed designs, when compared against the exact design, achieve an increment of 26.5% and 32.2% in power and power-delay-product, respectively, and when compared with other approximate designs, achieve an improvement of 18.4% and 26.4%, respectively. Finally, proposed designs are evaluated using image processing and neural network applications.