ABSTRACT The number of smart devices grows rapidly, and the main leakage of many of these devices is their limited batteries, in addition to the need for a fast and low-power computing system. Approximate calculations are an excellent method for such systems to achieve higher speed and less area and power consumption at the cost of lower accuracy. Furthermore, in many applications with inherent tolerance for insignificant inaccuracies such as image processing, approximate computing can be used to achieve acceptable performance with higher speed, lower power or area consumption. In this work, approximate multiplier structures are proposed based on working on the partial product trees with the aim of reducing area consumption and increasing accuracy. Comprehensive experimental analysis is performed to evaluate the performance of the proposed multiplier in terms of area, delay, power consumption, and accuracy. The results show that our suggested design improves at most 29% of power consumption, 11% of delay, and 55% of the area rather than an exact multiplier. Moreover, the performance of our multipliers is investigated based on the peak signal noise ratio (PSNR) for processing two images, which lead to 56.65 and 23.6 dB.

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