Design of High Speed and Low Power Approximate Multiplier for Image and Digital Signal Processing Applications

Abstract

Truncation based approximate multiplier is a scalable multiplier in which truncation is performed based on the leading one bit positions in each and every input operands, hence the number of partial products are reduced. In this multiplier design the multiplication process is done by addition, shifting and multiplication processes which has a very good improvement in space occupation and power consumption when compared to the exact multiplier. To enhance the multipliers speed each and every input operand in the multiplication side are truncated using the method given below. Based upon the leading 1’s the input operands, the inputs are truncated show that the accuracy does not depend on input operand’s width. Hence this multiplier is scalable. Very large improvement in multiplier’s design parameters like power and area consumption are obtained which is independent of the width of the input operand. To find the working efficiency of this multiplier we have compared the design parameters with some recently proposed multipliers and the exact multiplier. They obtained result states that the proposed multiplier enhances power consumption, delay and area up to 90%, 80% and 95% when compared to be exact multiplier. Also our design outsmarts other multipliers in parameters like power consumption, speed and area. Proposed approximate multiplier has zero mean value Gaussian distribution. We have figured it out it by MATLAB applications and a good PSNR and MSE is obtained. The output shows that the degradation in quality is almost negligible. Also we recommend Truncation based approximate multiplier where power consumption has to be adjusted in multiplication operation.