Analog Signal Processing Applications Research Articles

CMOS four-quadrant multiplier using active attenuators

Abstract A new CMOS four-quadrant multiplier using active attenuators is presented. Simulation results show that for a power supply of ±5 V, the linear range is over + 1 V with the linearity error less than 0-83%. The total harmonic distortion is less than 1% with an input range up to ± 1 V. The simulated —3dB bandwidth is about 5 MHz. Experimental results show that the linear range is within ± 1 V. The proposed multiplier is expected to be useful in analogue signal processing applications.

CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs

A CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs is presented. Experimental and simulation results are given to verify the theoretical analyses. Simulation results show that the nonlinearity error of the multiplier is less than 1% with an input range up to 70 mV. Its total harmonic distortion is less than 1% with an input range up to 50 mV. The simulated bandwidth is about 330kHz. The proposed 'squarer’ was built and tested using discrete CMOS transistor arrays. The proposed circuits are expected to be useful in analogue signal processing applications.

CMOS analog divider and four-quadrant multiplier using pool circuits

CMOS divider and four-quadrant multiplier circuits using the pool circuits are presented. Using CMOS differential amplifiers and MOS transistors biased in the saturation region, the new analog divider and multiplier are presented. Experimental and simulation results are given-to verify the theoretical analyses. The proposed circuits are expected to be useful in analog signal processing applications. >

Square-rooting and vector summation circuits using current conveyors

New analogue squaring, square-rooting and vector summation circuits using current conveyors (CCIIs) are presented. They consist of MOS transistors biased in the triode region, a buffered unity-gain inverting amplifier, resistors and CCIIs. A general n-input vector summation circuit is also proposed. The proposed squaring, square-rooting circuits and a two-input vector summation circuit have been implemented using commercial CCIIs and transistor arrays. Its -3 dB bandwidth is measured to be about 400 kHz. The proposed circuits are expected to be useful in analogue signal-processing applications.

CMOS squarer and four-quadrant multiplier

A CMOS squarer and a four-quadrant multiplier using the MOS transistors operated in saturation are presented. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over /spl plusmn/2 V input range and a -3 dB bandwidth of 5 MHz. The total harmonic distortion is less than 2.5% with input range up to /spl plusmn/2 V. The squarer has a nonlinearity error less than 1% over /spl plusmn/1.95 V input range. The second-order effect caused by the mobility reduction is discussed. The proposed circuits will be useful in analog signal-processing applications. >

Low voltage CMOS four-quadrant multiplier

A new low voltage CMOS four-quadrant multiplier is presented. Simulation results show that, for a power supply of ±1.5 V the differential linear range is over ±0.8V with the linearity error less than 2%. The total harmonic distortion is less than 1% with the input range up to ±0.6 V. The simulated –3 dB bandwidth of this multiplier is about 12 MHz. The proposed circuit is expected to be useful in low-voltage analogue signal processing applications.

Design and applications of a CMOS analog multiplier cell using the differential difference amplifier

This paper presents design techniques for a wide input range CMOS differential difference amplifier (DDA) and discusses its application as a basic block in the implementation of a simple four-quadrant multiplier cell. The cell can be configured as an amplitude modulator or a one-over circuit, which are widely used in many analog signal processing applications. The DDA can also be reconfigured as an opamp, and hence can be used to design many of the opamp-based multiplier circuits. The DDA amplitude modulator (AM) uses a transistor and a resistor as the only components external to the DDA. A DDA one-over circuit, which provides an output proportional to the inverse of the input, is also achieved with the same level of simplicity. High-frequency effects due to the DDA's finite gain-bandwidth (GB) and MOS parasitic capacitances are investigated. Experimental results obtained from a 2µm CMOS MOSIS chip are given.

CMOS four-quadrant multiplier using bias feedback techniques

A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of /spl plusmn/5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over /spl plusmn/1 V. The results will be useful in analog signal processing applications. >

A very high-frequency CMOS complementary folded cascode amplifier

A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm/sup 2/), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF. >

Fully balanced CMOS current-mode circuits

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2- mu m n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2- mu m p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with V/sub dd/ 5 V. >

CMOS four-quadrant multiplier using bias offset crosscoupled pairs

A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that for a power supply of ±5 V, the linearity error is less than 1% over a ±2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.

A nonlinear CMOS analog cell for VLSI signal and information processing

A simple reconfigurable continuous-time nonlinear CMOS building block for analog VLSI applications is presented. The new block is introduced as a basic analog cell for the implementation of analog VLSI systems. It simultaneously achieves four-quadrant multiplication and division. Its applications in both analog signal and information processing are discussed. These include multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-DC conversion, and neural computing. Using the new cell, a MOS VLSI implementation of a feedback/feedforward neural network is developed which achieves the scalar product of two n-tuple vectors by 4(n+1) MOS transistors and one operational amplifier. To verify the versatility of the new cell and its applications, experimental results obtained from a test chip that was fabricated using the MOSIS 2- mu m CMOS process are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Precision switched-capacitor attenuator

The problem of capacitor mismatch error in a switched-capacitor voltage divider (attenuator) is addressed. It is shown that, with the help of a ratio-independent voltage multiplier (amplifier) proposed earlier, it is possible to make the error in the voltage divider arbitrarily small, at the expense of time. This precision voltage divider is expected to be useful in a wide range of precision analog signal-processing applications.

A reflex optoelectronic switching matrix

A novel method of rapidly composing any required signal delay or combination of delays from a set of precise fixed delay lines is described. Both simple delays and recirculating delay loops can be obtained. The construction of programmable ring resonators with both optical and electrical delay lines is demonstrated. Tunable comb filters with bandwidths up to 1 GHz were obtained. Since delays can be altered within nanoseconds, many applications in digital and analog signal processing can be realized.

Reactive ion etching in the fabrication of niobium tunnel junctions

A niobium-based tunnel-junction technology has been developed for analog signal-processing applications. Devices of interest would integrate superconductive transmission lines and superconductor/insulator/superconductor (SIS) mixers. Reactive ion etching of niobium patterns with linewidths of 1 μm or less has been investigated with regard to the composition of gases, chamber pressure and power levels. These studies were made on RF-sputtered niobium films having critical-transition temperatures above 9°K. Junction area is defined by reactively ion etching insulating films of silicon monoxide to resolutions of 0.3μm or better. A niobium-oxide tunnel barrier is grown by RF-plasma oxidation. Proper control of the technology has allowed the achievement of critical current densities which are uniform to 10% or better over the silicon substrate. Junction V-I characteristics show low leakage currents with critical current densities to 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Lead is employed for counter-electrodes and indium-gold (or aluminum) for circuit resistors. The robustness and stability of niobium-based junctions is essential in applications which normally require extreme dependability and long standby times.

High-speed InP optoelectronic switch

The successful fabrication and demonstration of an InP optoelectronic switch is reported. The results obtained suggest that this device may be better suited for high-speed analog signal processing applications than previously reported Si and GaAs switches. In experiments using cw mode-locked lasers, the switches have exhibited an on-state impedance of 45 Ω for 40pJ of incident laser energy and an inherent rise time of 30 psec. In addition, the switches have been used to generate a train of 70-psec-wide pulses at a 900-MHz repetition rate, and to sample a 68.9-MHz sine wave at 275 MS/sec with an accuracy to 0.2 dB (98%) and an on-off ratio of 40 dB.

Charge-coupled devices for wideband quadrature networks

Charge-coupled devices (CCD) are relatively new electronic devices which hold out great promise in a wide range of digital and analogue signal processing applications. This paper examines the suitability of the CCD as the delay elements in a quadrature network. Some experimental results are included.

A [formula omitted] CCD compatible process for analog signal processing applications : R. Dawson, J. Preisig, J. Carnes and J. Pridgen. RCA Rev.38, 406 (September 1977)

A [formula omitted] CCD compatible process for analog signal processing applications : R. Dawson, J. Preisig, J. Carnes and J. Pridgen. RCA Rev.38, 406 (September 1977)

Charge handling capacity in charge coupled devices

In analog signal processing applications, the charge handling capacity of a charge coupled device (CCD) is an important parameter that determines the dynamic range. In this paper, approximate expressions for the signal handling capacity for surface-channel and buried-channel CCD's are derived and compared. The upper limit for the buried-channel charge capacity is imposed by the onset of surface electron accumulation.

A dual differential charge-coupled analog delay device

A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated d.c. offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV r.m.s. input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55/spl deg/C.