CMOS squarer and four-quadrant multiplier

Abstract

A CMOS squarer and a four-quadrant multiplier using the MOS transistors operated in saturation are presented. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over /spl plusmn/2 V input range and a -3 dB bandwidth of 5 MHz. The total harmonic distortion is less than 2.5% with input range up to /spl plusmn/2 V. The squarer has a nonlinearity error less than 1% over /spl plusmn/1.95 V input range. The second-order effect caused by the mobility reduction is discussed. The proposed circuits will be useful in analog signal-processing applications. >